DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 16/724,710, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. The limitation of original claim 8, currently amended in claim 1 is not entitled to the benefit of the prior application.
Allowable Subject Matter
The indicated allowability of claims 1-4, 6, 7, 9, 10, 13-21 are withdrawn in view of the newly discovered reference(s) to Buford (US Pub no. 2020/0343301 A1). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 6, & 7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support for “wherein a width of the second conductive layer over the lower via is greater than a width of the lower via and less than a width of the memory cell” as described in claim 1. Para[0003] of the specification states: It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Furthermore, the specification mentions in para [0071] “in some embodiments, the MTJ structure 120, the SOT layer 112, and/or the shunting layer 114 may be patterned such that the widths of the SOT layer 112 extending laterally beyond the MTJ structure 120 are minimized and/or eliminated”. However, there is no support for the width of the second conductive layer compared to the width of the memory cell and via. Consequently, the current amendment to claim 1 is not entitled to the benefit of the filing date of the parent application, and the effective filing date is 11/8/2022.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-21 & 24-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 16, the limitation of including: “wherein first opposing sidewalls of the second conductive layer are aligned with the first opposing sidewalls of the first conductive layer and second opposing sidewalls of the second conductive layer are aligned with the second opposing sidewalls of the second conductive layer” is unclear. The structure of the device is unclear because it defines the position of a feature by referring back to itself. The second opposing sidewalls of the second conductive layer cannot be aligned with itself because it fails to provide spatial relationship to the claimed components of the device structure. Therefore, one skilled in the art would be unable to determine the scope of the claimed invention.
Appropriate correction is required.
With regards to claim 25, the limitation of including: wherein a width of the electrode is substantially equal to a width of the electrode is unclear. The structure of the device is unclear because it defines the position of a feature by referring back to itself. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16, 17, & 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Buford (US Pub no. 2020/0343301 A1)
Regarding claim 16, Buford et al discloses A method for forming an integrated circuit (IC),comprising: forming a first via (126)over a substrate(138)[0057][0070];
forming a first conductive layer(102) over a top surface of the first via(126)[0057] fig. 1a/1b, wherein the first conductive layer(102) comprises first opposing sidewalls elongated in a first direction and second opposing sidewalls elongated in a second direction substantially orthogonal to the first direction fig. 1a/1B;
forming a memory cell (106)on a top surface of the first conductive layer(102)[0054], wherein the memory cell (106) is laterally offset from the first via(126) by a first distance TCM1[0057] ; and forming a second conductive layer(122) on the top surface of the first conductive layer(102)[0055], wherein the second conductive layer(122) directly overlies the first via(126) fig.1a, wherein an area of a bottom surface of the second conductive layer(122) is greater than an area of the top surface of the first via(126) (fig. 1b) , wherein first opposing sidewalls of the second conductive layer(122) are aligned with the first opposing sidewalls of the first conductive layer (106)and second opposing sidewalls of the second conductive layer(122) are aligned with the second opposing sidewalls
of the second conductive layer(122) fig. 1a/1b.
Regarding claim 17, Buford et al discloses further comprising: forming a first sidewall spacer (110-110a)on the top surface of the first conductive layer(102) and along sidewalls of the memory cell(106), wherein the first sidewall spacer(110-110a) is formed before forming the second conductive layer(122)[0054][0055].
Regarding claim 19, Buford et al discloses further comprising: forming a second via (130)over the substrate(138)[0070][0057], wherein the first conductive layer(102) continuously laterally extends from the top surface of the first via (126)to a top surface of the second via(130) fig. 1a/1b, wherein the second conductive layer (122)directly overlies the top surface of the second via(130); and forming an upper via(620) over the memory cell(106), wherein the second conductive layer(122) is laterally offset from sidewalls of the upper via(620)(fig. 10b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1- 4, 6, 7, 9, 10, 13-15 & 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buford (US Pub no. 2020/0343301 A1)
Regarding claim 1, Buford et al discloses A semiconductor structure comprising: a memory cell (106)overlying a substrate(138)[0054]; a lower via(126) underlying the memory cell(106), wherein the lower via(126) is laterally offset from the memory cell(106) by a lateral distance(Tcm1)[0057] fig. 1; a first conductive layer(102) disposed vertically between the memory cell(106) and the lower via (126)and comprising a first material, wherein the first conductive layer (102)continuously extends along the lateral distance fig. 1a; and a second conductive layer(122) extending across an upper surface of the first conductive layer(102) and comprising a second material different from the first material[0062][0065], wherein a bottom surface of the second conductive layer(122) is aligned with a bottom surface of the memory cell(106) fig. 1a. Buford et al discloses a thickness of the second conductive layer(122) and a thickness of the first conductive layer (102) [0060][0063] and wherein a width of the second conductive layer(122) over the lower via(126) is greater than a width of the lower via(126) fig. 1b and a width of the memory cell (106)[0076] but fails to teach wherein a thickness of the second conductive layer is greater than a thickness of the first conductive layer ; and wherein a width of the second conductive layer is less than a width of the memory cell. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to achieve a thickness of the second conductive layer being greater than a thickness of the first conductive layer through routine experimentation to optimize the electrical resistance in the second conductive layer[0062]. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, in another embodiment, Buford et al discloses wherein a width of the second conductive layer is less than a width of the memory cell[0053]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the embodiment of fig. 1a-1d with the teachings of Buford et al [0053] to optimize the spin hall current.
Regarding claim 2, Buford et al discloses wherein the memory cell (106)comprises a free layer(300), a tunnel barrier layer(302), and a reference layer(304), wherein a bottom surface of the free layer (300)defines the bottom surface of the memory cell(106)[0095-0097].
Regarding claim 3, Buford et al discloses wherein the second conductive layer (122)continuously laterally surrounds an outer perimeter of the memory cell(106) fig. 1b.
Regarding claim 4, Buford et al discloses further comprising: a sidewall spacer structure (110)disposed around the outer perimeter of the memory cell(106), wherein the sidewall spacer structure (110)continuously extends from the outer perimeter
of the memory cell (106)to an inner perimeter of the second conductive layer(122), wherein a bottom surface of the sidewall spacer structure(110) is aligned with the bottom surface of the second conductive layer(122) fig. 1a/1b.
Regarding claim 6, Buford et al discloses wherein the memory cell (106)comprises a data storage structure (300)[0095]and wherein a top surface of the second conductive layer(122) is vertically above a top surface of the data storage structure(300)[0095][0060].
Regarding claim 7, Buford et al discloses wherein an area of the bottom surface of the second conductive layer (122)is greater than an area of a top surface of
the lower via(126 ) fig. 1b.
Regarding claim 9, Buford et al discloses An integrated circuit (IC) comprising: a first via (126)overlying a substrate(138); a second via(130) overlying the substrate(138) and laterally separated from the first via(126) by a
first distance[0057]; a first conductive layer (102) overlying the first via(126) and the second via(130)[0057], wherein the first conductive layer (102)continuously laterally extends from the first via(126) to the second via (130)along
the first distance[0057]; a first memory cell (106)disposed on a top surface of the first conductive layer(106)[0057], wherein the first memory cell(106) is laterally offset from the first via(126), and wherein the first conductive layer(102) continuously laterally extends from a top surface of the first via(126) to a bottom surface of the first memory cell(106)[0057]; a second memory cell (114)disposed on the top surface of the first conductive layer(102), wherein the second memory cell (114)is disposed laterally between the first memory cell (106)and the second via(130)[0057]; and a second conductive layer (122)disposed on the top surface of the first conductive layer(102), wherein the second conductive layer (122)directly overlies the top surface of the first via(126) and the second via(130)[0057-0058], wherein the second conductive layer(122) is disposed laterally between the first memory cell (106)and the second memory cell(114), wherein the first memory cell (106)is laterally offset from the first via(126) by a second distance(TCm1), wherein the second distance(TCm1) is non-zero and less than a width of the first memory cell(106)[0057-0059], and wherein the first memory cell (106)is offset from the second memory cell (114)by a third distance (WM1M2)[0056-0057]but fails to teach that is greater than the second distance(TCm1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve the third distance that is greater than the second distance through routine experimentation to optimize the current electrical path. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 10, Buford et al discloses wherein the second conductive layer(122) is disposed vertically between a top surface and the bottom surface of the first memory cell(106) fig. 1a.
Regarding claim 13, Buford et al discloses wherein a resistance of the second conductive layer(122) is less than a resistance of the first conductive layer(102).
Regarding claim 14, Buford et al discloses further comprising: a sidewall spacer(110) disposed along sidewalls of the first memory cell(106), wherein a
bottom surface of the sidewall spacer(110) is aligned with a bottom surface of the second conductive layer(122) fig. 1a.
Regarding claim 15, Buford et al discloses wherein the sidewall spacer (110)directly contacts a sidewall of the second conductive layer(122) and directly contacts a sidewall of the first memory cell(106) fig. 1a.
Regarding claim 21, Buford et al discloses wherein in top view the second conductive layer(122) laterally encloses an outer perimeter of the first memory cell (106)and an outer perimeter of the second memory cell(114) fig. 1a/1b.
Claim(s) 18 & 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buford (US Pub no. 2020/0343301 A1) in view of O’Brien (US Pub no. 2019/0304523 A1).
Regarding claim 18, Buford et al discloses all the claim limitations of claim 17 but fails to teach further comprising: forming a second sidewall spacer along sidewalls of the first conductive layer, wherein the first sidewall spacer and the second sidewall spacer are formed concurrently.
However, O’ Brien et al discloses a SOT memory device comprising forming a second sidewall spacer (470C)along sidewalls of the first conductive layer(201),wherein the first sidewall spacer(470A) and the second sidewall spacer(470C) are formed concurrently[0095][0098].It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Buford et al with the teachings of O’Brien et al to provide protection during subsequent processing steps.
Regarding claim 24, Buford et al discloses all the claim limitations of claim 16 and further teaches wherein forming the memory cell(106) and the first conductive layer(102) comprises: depositing a conductive film(600) over the first via(126)[0113-0114]; depositing a memory structure(106/114) over the conductive film(600) [0115]; forming a hard mask over the memory structure; performing a first etch on the memory structure (106/114)to remove portions of the memory structure laterally offset from the hard mask (mask)in the first direction[0115], wherein the first etch stops on the conductive film (600) fig. 6b[0115]but fails to teach performing a second etch on the memory structure and the conductive film to form the memory cell and the first conductive layer, respectively, wherein the second etch forms the first opposing sidewalls and the second opposing sidewalls of the first conductive layer.
However, O’Brien et al discloses performing a second etch on the memory structure (210)and the conductive film(201b) to form the memory cell and the first conductive layer(201b)[0088], respectively, wherein the second etch forms the first opposing sidewalls and the second opposing sidewalls of the first conductive layer(201b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Buford et al with the teachings of O’Brien et al since the density of SOT memory devices per unit area may be increased.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buford (US Pub no. 2020/0343301 A1) in view of Yoda (US Pub no 2017/0169872 A1).
Regarding claim 20, Buford et al discloses all the claim limitations of claim 16 and further teaches wherein a top surface of the second conductive layer (122) is below a top surface of the memory cell(106) fig. 1a/1b but fails to teach wherein a thickness of the second conductive layer is at least half a thickness of the memory cell.
However, Yoda et al discloses wherein a thickness of the second conductive layer(50) is at least half a thickness of the memory cell(20)[0150][0155] fig 17. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Buford et al with the teachings of Yoda et al to prevent an adverse effect of a voltage effect and to lower energy consumption further.
Claim(s) 25 & 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buford (US Pub no. 2020/0343301 A1) in view of Kanaya (US Pub no. 2015/0069480 A1).
Regarding claim 25, Buford et al discloses all the claim limitations of claim 16 but fails to teach forming a conductive wire over the first via; forming an electrode between the conductive wire and the first conductive layer, wherein a width of the electrode is substantially equal to a width of the electrode.
However, Kanaya et al discloses forming a conductive wire (51)over the first via(50); forming an electrode(15) between the conductive wire (51), wherein a width of the electrode(15) is substantially equal to a width of the electrode(15)[0081]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Buford et al with the teachings of Kanaya et al such that a conductive wire over the first via; forming an electrode between the conductive wire and the first conductive layer, wherein a width of the electrode is substantially equal to a width of the electrode results to promote crystal growth.
Regarding claim 26, Buford et al discloses Buford et al discloses a thickness of the second conductive layer(122) and a thickness of the first conductive layer (102) [0060][0063] but fails to teach a thickness of the second conductive layer is greater than a thickness of the first conductive layer and less than a thickness of the electrode. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to achieve a thickness of the second conductive layer being greater than a thickness of the first conductive layer through routine experimentation to optimize the electrical resistance in the second conductive layer[0062]. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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