DETAILED ACTION
This correspondence is in response to the communications received 02/26/2026. Claims 1, 4-6, 10, 14-23 have been amended. Claims 1-23 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/07/2026 has been considered by the examiner and made of record in the application file.
Response to Amendment
Applicant’s amendment to the drawings overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendment to claim 4 overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendment to claim 5 overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendments to claims 15 and 22 overcome the objection outlined in the previous Office Action. The objection is withdrawn. However, the amendment to claim 15 introduces a new informality that is objected to below.
Applicant’s amendments to claims 16 and 17 overcome the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendments to claims 18 and 23 overcome the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendment to claim 21 overcomes the objection outlined in the previous Office Action. The objection is withdrawn. However, the amendment to claim 21 introduces a new informality that is objected to below.
Applicant’s amendment to claim 1 overcomes the double patenting rejection outlined in the previous Office Action. The rejection is withdrawn.
Applicant’s amendments to claims 1, 6, 10, 15, and 20 overcome the 112(b) rejection outlined in the previous Office Action. The rejection is withdrawn.
Applicant’s amendment to claim 5 overcomes the 112(b) rejection outlined in the previous Office Action. The rejection is withdrawn.
Applicant’s amendment to claim 14 overcomes the 112(b) rejection outlined in the previous Office Action. The rejection is withdrawn.
Applicant’s amendments to claims 18 and 23 overcomes the 112(b) rejection outlined in the previous Office Action. The rejection is withdrawn.
Applicant’s amendment to claim 19 overcomes the 112(b) rejection outlined in the previous Office Action. The rejection is withdrawn.
Response to Arguments
The Examiner appreciates the use of colored annotations in the Remarks/Arguments. However, as all the documents in the application’s file wrapper are converted to black and white, the colored annotations are not able to be used as a reference.
In the Response to Restriction filed 09/23/2025, the Applicant elected species B without traverse. As noted in the Requirement for Restriction/Election of 07/24/2025, species B corresponds to Figs. 16A-30B. Therefore, any arguments relying on figures from non-elected species are not applicable.
As the argument regarding the 112(b) rejection of claim 21 relies on a figure from a non-elected species, species A, the argument is not applicable and the rejection is maintained.
Applicant's arguments filed 02/26/2026 with respect to the 102 rejection of claim 15 on pages 21 and 22 of the remarks, have been fully considered but they are not persuasive.
Applicant asserts that Wang et al. (US 10,497,577 B2) does not disclose or otherwise suggest all the limitations of newly amended claim 1. Specifically, that the isolation wall interpretated as “capping layer 83” (col. 5, line 64) of Wang is not “in level up to the top surface of the fin structure” where the fin structure is interpreted as “fins 64” (col. 5, line 65) of Wang.
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However, the amended claim language uses the phrase “in level up to a top surface”, where “up to” is a broad term that includes any position below the top surface of the fin structure, and is not limited to only features at the exact height of the top surface of the fin structure. As seen in Fig. 21B, a top surface of 83 is below a top surface of 64. Thus, Wang discloses “a top surface of the isolation wall is in level up to a top surface of the fin structure.
Applicant’s arguments filed 02/26/2026 with respect to the 103 rejection of claim 20 on pages 27-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 02/26/2026 with respect to the 103 rejection of claim 15 on pages 31 and 32 of the remarks, have been fully considered but they are not persuasive.
Applicant asserts that neither Wang et al. (US 10,497,577 B2) nor Kim et al. (US 10,147,650 B2) disclose or otherwise suggest all the limitations of newly amended claim 15. Specifically, that the sides of a first conductive region interpretated as “first epitaxial layer 120” (col. 10, line 8) of Kim connect to a metal region interpretated as the “metal contact 150” (col. 10, line 8) also of Kim, thereby allegedly precluding a first sidewall of 120 from being opposite from a second sidewall of 120, wherein at least the first sidewall of 120 connects to 150.
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However, the first sidewall of 120 seen in Fig. 2 as the instance of “SW” on the left side of 120 is connected to 150 and opposite the second sidewall of 120 seen in Fig. 2 as the instance of “SW” on the right side of 120. Thus, Kim discloses “the first sidewall is opposite to the second sidewall; wherein at least the first sidewall of the first conductive region connects to a metal region”.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 is objected to because of the following informalities: After amendment, line 6 of claim 1 now reads “wherein a top surface of the isolation wall is in level up to a top surface of the fin structure;.” The extraneous semicolon should be removed. Appropriate correction is required.
Claim 15 is objected to because of the following informalities: Claim 15 recites “wherein at least the first sidewall of the first conductive region connect to a metal region”, this limitation should be written as “wherein at least the first side wall of the first conductive region connects to a metal region”. Appropriate correction is required.
Claim 21 is objected to because of the following informalities: Claim 21 recites "wherein the bottom of the gate region over the shallow trench isolation region is lower the bottom of the first conductive region by more than 10nm". It appears this limitation should be written as "wherein the bottom of the gate region over the shallow trench isolation region is lower than the bottom of the first conductive region by more than 10nm". Appropriate correction is required.
Claim Interpretation
Claims 1, 6, 10, 15, and 20 use the phrase “to fix the fin structure”. Merriam-Webster defines “to fix” as “to make firm, stable, or stationary”. Therefore, any physical feature that may help to reinforce the fin structure may also be said to fix it. This is not limited to elements in direct contact with the fin structure, but rather includes any elements that appear to add some structural rigidity to the fin structure.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 21, the phrase "the bottom of the gate region over the shallow trench isolation region" renders the claim indefinite because it is unclear as to how the bottom of the gate region is over the shallow isolation trench. As seen in Fig. 30A, “STI-oxide2 2102” horizontally overlaps the gate region, interpreted as “Hi-K dielectric layer 1902", "gate material 2002", "nitride-1 layer 5062", and "Hardmask-oxide layer 5064". In Fig. 30A, even the bottom of the uppermost portion of the gate region, 5064, is still below part of 2102.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, transistor structure comprising:
a substrate (" p-type substrate 200") with a fin structure (see Fig. 20 (a));
an isolation wall (together "thermal-oxide-1 layer 2003", "nitride-1 spacer 2004", and "oxide-2 spacer 2006" form an isolation wall) covering and surrounding sidewalls of the fin structure to fix the fin structure, wherein a top surface of the isolation wall is in level up to a top surface of the fins structure (see Fig. 20 (a)); and
a gate region (together "Hi-K dielectric layer 1902", "gate material 2002", "nitride-1 layer 5062", and "Hardmask-oxide layer 5064" form a gate region) above the fin structure and the isolation wall (see Fig. 30A).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 1-3, 5-7, and 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Wang et al. (US 10,497,577 B2, hereinafter “Wang”).
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Regarding claim 1, Figs. 2-21B of Wang disclose a transistor structure (“FinFET device 100”, col. 2, line 37) comprising:
a substrate (“substrate 50”, col. 2, line 49) with a fin structure (“semiconductor fins 64 (e.g., 64A and 64B)”, col. 4, line 67, and col. 5, line 1);
an isolation wall (“capping layer 83”, col. 5, line 63, as seen in Fig. 12, 83 physically isolates 64 from “dielectric layer 85”, col. 8, lines 1-2, “top layer 87”, col. 7, line 63, and “insulation material 62”, col. 7, line 13) covering and surrounding sidewalls of the fin structure (as seen in Fig. 12, 83 covers and surrounds sidewalls of 64A and 64B) to fix the fin structure (as seen in Fig. 12, 83 buttresses the base of 64A and 64B, thereby adding structural rigidity and fixing 64A and 64B in place), wherein a top surface of the isolation wall is in level up to a top surface of the fin structure (as seen in Fig. 21B, a top surface of 83 is below a top surface of 64, thus a top surface of 83 is in level up to a top surface of 64); and
a gate region (together “first replacement gate 99A”, col. 14, lines 60-61, “second replacement gate 99B”, col. 14, line 63, “contacts 102”, col. 14, line 67, and “second interlayer dielectric (ILD) 95”, col. 13, line 59, is a gate region, where 99A is “comprising gate dielectric 96/barrier layer 94/seed layer 92/gate electrode 98A”, col. 14, lines 61-62 and 99B is “comprising gate dielectric 96/barrier layer 94/seed layer 92/gate electrode 98B”, col. 14, lines 63-65) above the fin structure (as seen in Fig. 21B, 99A and 99B are above 64);.
Regarding claim 2, Figs. 2-21B of Wang disclose the transistor structure of claim 1, Figs. 2-21B of Wang further disclose wherein the isolation wall clamps four sidewalls of the fin structure (as seen in in Fig. 12, 83 clamps four sidewalls of 64)
Regarding claim 3, Figs. 2-21B of Wang disclose the transistor structure of claim 2, Figs. 2-21B of Wang further disclose further comprising a shallow trench isolation (STI) layer (“recessed insulation material 62 forms isolation regions 62, such as shallow trench isolation (STI) regions”, col. 9, lines 23-24) surrounding the isolation wall (as seen in in Fig. 12, 62 surrounds 83).
Regarding claim 5, Figs. 2-21B of Wang disclose the transistor structure of claim 2, Figs. 2-21B of Wang further disclose wherein the gate region comprises a gate dielectric layer (“gate dielectric 96”, col. 12, line 53) over the fin structure substrate (as seen in Fig. 21B, 96 is over 64 and 50), a gate conductive layer (“gate electrode 98A”, col. 14, line 62, and “gate electrode 98B”, col. 14, line 62, electrodes are known in the art as conductive) over the gate dielectric layer (as seen in Fig. 21B, 98A and 98B are over 96), and a cap layer (“second interlayer dielectric (ILD) 95”, col. 13, line 59) over the gate conductive layer (as seen in Fig. 21B, 95 is over 98A and 98B).
Regarding claim 6, Figs. 2-21B of Wang disclose the transistor structure of claim 5, Figs. 2-21B of Wang further disclose wherein the isolation wall is configured to fix the fin structure during the formation of the gate dielectric layer, the gate conductive layer, and the cap layer (as seen in Fig. 21B, 83 was formed prior to the formation of 96, 98A, 98B, and 95, therefore the functionality attributed to 83 described above is also applicable during the formation of 96, 98A, 98B, and 95, furthermore in Fig. 21B, Wang shows 83 with 64 intact thus matching the claimed structural characteristics, the implied sequence of forming the isolation wall prior to forming the gate elements is considered to be a product by process limitation).
"[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted), see MPEP 2113. I.
Regarding claim 7, Figs. 2-21B of Wang disclose the transistor structure of claim 1, Figs. 2-21B of Wang further disclose further comprising a spacer layer (“second gate spacer 73”, col. 11, line 4) on a sidewall of the gate region (as seen in Fig. 13, 73 is on the sidewalls of what will become 99A or 99B).
Regarding claim 20, Figs. 2-21B of Wang disclose a transistor structure (“FinFET device 100”, col. 2, line 37) comprising:
a substrate (“substrate 50”, col. 2, line 49) with a fin structure (“semiconductor fins 64 (e.g., 64A and 64B)”, col. 4, line 67, and col. 5, line 1);
an isolation wall (“capping layer 83”, col. 5, line 63, as seen in Fig. 12, 83 physically isolates 64 from “dielectric layer 85”, col. 8, lines 1-2, “top layer 87”, col. 7, line 63, and “insulation material 62”, col. 7, line 13) covering and surrounding sidewalls of the fin structure (as seen in Fig. 12, 83 covers and surrounds sidewalls of 64A and 64B) to fix the fin structure (as seen in Fig. 12, 83 buttresses the base of 64A and 64B, thereby adding structural rigidity and fixing 64A and 64B in place);
a shallow trench isolation (STI) region (together “recessed insulation material 62”, col. 9, line 23 and “first interlayer dielectric (ILD) 90”, col. 12, lines 23-24 form an STI region where “recessed insulation material 62 forms isolation regions 62, such as shallow trench isolation (STI) regions”, col. 9, lines 23-24, and as 90 is a dielectric material in a recess, seen in Fig. 21B, it can also be interpretated as an STI region) surrounding the fin structure (as seen in Fig. 21B, 62 surrounds 64A and 64B);
a gate region (together “first replacement gate 99A”, col. 14, lines 60-61, “second replacement gate 99B”, col. 14, line 63, “contacts 102”, col. 14, line 67, and “second interlayer dielectric (ILD) 95”, col. 13, line 59, is a gate region, where 99A is “comprising gate dielectric 96/barrier layer 94/seed layer 92/gate electrode 98A”, col. 14, lines 61-62 and 99B is “comprising gate dielectric 96/barrier layer 94/seed layer 92/gate electrode 98B”, col. 14, lines 63-65) above the fin structure (as seen in Fig. 21B, 99A and 99B are above 64); and
a first conductive region (“source/drain regions 80”, col. 11, line 41, source/drain features are known in the art as conductive) abutting against the fin structure (as seen in Fig. 14A, 80 abuts 64);
wherein a bottom of the gate region located on the STI region and outside the fin structure is lower than a top surface of the STI region outside the gate structure (as seen in Fig. 21B, a bottom of 99A is located on 62 and outside 64A and is also lower than a top surface of 90 which is also outside 64A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 10,497,577 B2, hereinafter “Wang”) in view of Wu et al. (US 8,890,207 B2, hereinafter “Wu”).
Regarding claim 4, Figs. 2-21B of Wang disclose the transistor structure of claim 1.
Wang fails to disclose “further comprising a sheet channel layer disposed between the sidewalls of the fin structure and the isolation wall, wherein the sheet channel layer is formed by a selective epitaxy growth technique.”
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However, in a similar field of endeavor, Figs. 3A-11C of Wu teach further comprising a sheet channel layer (“first capping layer 151”, col. 3, lines 38-39, as seen in Fig. 6B, 151 is a thin layer and is therefore a sheet, further “first capping layer 151 may be used to help keep the channel carriers within a thin layer underneath the gate resulting in improved electrostatic control of the gate”, col 3, lines 19-21) disposed between the sidewalls of the fin structure (“fin 150”, col. 2, line 63, 150 of Wu is equivalent to 64 of Wang) and the isolation wall (as 151 must be directly on 150 in order to achieve the improved electrostatic control, after substitution of 151 of Wu into the system of Wang, 151 of Wu will be between 64 and 83 of Wang), wherein the sheet channel layer is formed by a selective epitaxy growth technique (“the first capping layer 151 is epitaxially grown on the exposed portion of the fin 150 by selective epitaxial growth (SEG)”, col. 3, lines 38-39).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising a sheet channel layer disposed between the sidewalls of the fin structure and the isolation wall, wherein the sheet channel layer is formed by a selective epitaxy growth technique” as taught by Wu in the system of Wang for the purpose of improving electrostatic control of the gate.
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 10,497,577 B2, hereinafter “Wang”) in view of Mehandru et al. (US 11,688,780 B2, hereinafter “Mehandru”, while US 11,688,780 B2 is used for reference convenience, the contents were previously published 2020-09-24 as US 20200303509 A1).
Regarding claim 8, Figs. 2-21B of Wang disclose the transistor structure of claim 7, Figs. 2-21B of Wang further disclose further comprising a first conductive region (together “source/drain regions 80”, col. 11, line 41 and “lightly doped drain (LDD) regions 65”, col. 10, lines 41-42, are a first conductive region, source/drain features are known in the art as conductive) abutting against the fin structure (as seen in Figs. 13 and 14A, 65 is abutting 64), wherein the first conductive region is independent from the substrate (“source/drain regions 80 are formed by etching the LDD regions 65 within the fins 64 to form recesses, and epitaxially growing a material in the recess”, col 11, lines 42-44, thus 80 are epitaxially grown independent from 50. While Wang does disclose 80 as being independent from 50, Wang does not disclose 65 as being independent from 50, instead 65 is formed through ion implantation of 50, see col 10, lines 42-43, instead a secondary reference will be used to teach lightly doped regions independent from the substrate).
Wang fails to disclose “wherein the first conductive region is independent from the substrate.”
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However, in a similar field of endeavor, Figs. 1-15 of Mehandru teach wherein the first conductive region is independent from the substrate (“source and/or drain semiconductor material 850 is advantageously lightly doped to have an electrically active impurity concentration that is higher than that of the channel region of bodies 206”, col. 10, lines 49-52, where 850 and 206 of Mehandru are equivalent to 65 and 64 of Wang respectively, further, “source and/or drain semiconductor material 850 is formed selectively on exposed portions of bodies 206 and/or substrate material layer 205”, col 10, lines 65-67, thus 850 of Mehandru is separate from 205, this technique could thus be applied to Wang resulting in both 65 and 80 of Wang to be formed independently of 50 of Wang)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement wherein the first conductive region is independent from the substrate as taught by Mehandru in the system of Wang for the purpose of forming lightly doped regions without the risk of contamination from an ion implantation process or potential damage associated with plasma processes.
Regarding claim 9, Figs. 2-21B of Wang in combination with Figs. 1-15 of Mehandru disclose the transistor structure of claim 8, Figs. 2-21B of Wang further disclose wherein the first conductive region is formed in a first concave (Using the technique of Mehandru, 65 and 80 are formed in a first concave, seen in Figs. 13 and 14A as the interface between 50/64 and 65, denoted “FC”) under an original surface of the substrate (the upper surface of 64 represents the original surface of 50, therefore as seen in Fig. 14A, 65 and 80 are formed below the original surface of 50).
Regarding claim 10, Figs. 2-21B of Wang in combination with Figs. 1-15 of Mehandru disclose the transistor structure of claim 9, Figs. 2-21B of Wang further disclose wherein the isolation wall is configured to fix the fin structure during the formation of the first concave and the first conductive region (as seen in Figs. 12 and 14A, 83 was formed prior to the formation of the upper surface of 65 and 80, therefore the functionality attributed to 83 described above is also applicable during the formation of the upper surface of 65 and 80, furthermore in Fig. 21B, Wang shows 83 with 64 intact thus matching the claimed structural characteristics, the implied sequence of forming the isolation wall prior to forming the first concave and the first conductive region is considered to be a product by process limitation).
"[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted), see MPEP 2113. I.
Regarding claim 11, Figs. 2-21B of Wang in combination with Figs. 1-15 of Mehandru disclose the transistor structure of claim 9, Figs. 2-21B of Wang further disclose wherein the first concave is formed by (1) etching the substrate to form a temporary concave on which a thermal oxide layer is then formed, and (2) etching the thermal oxide layer (“a mask layer, such as a pad oxide layer (not shown) and an overlying pad nitride layer (not shown), is formed over the substrate 51. The pad oxide layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process”, col. 4, lines 40-44, wherein “The patterned mask 58 is subsequently used to pattern exposed portions of the substrate 51 to form trenches 61, thereby defining semiconductor fins 64 (also referred to as fins) between adjacent trenches as illustrated in FIG. 4. In some embodiments, the semiconductor fins 64 (e.g., 64A and 64B) are formed by etching trenches in the substrate 51 using, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof”, col. 4, lines 63-67, col. 5, lines 1-3. After patterning, the pad oxide layer is a “patterned pad oxide 52”, col. 4, line 62. Wang does not disclose etching the substrate prior to forming the thermal oxide layer, however, the implied sequence of etching the substrate, forming the thermal oxide layer, then etching then thermal oxide layer is considered to be a product by process limitation).
"[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted), see MPEP 2113. I.
Regarding claim 12, Figs. 2-21B of Wang in combination with Figs. 1-15 of Mehandru disclose the transistor structure of claim 11, Figs. 2-21B of Wang further disclose wherein the first concave comprises a sidewall (as seen in Fig. 13, the portion of FC between 65 and 64 is a sidewall), the first conductive region comprises a lightly doped region (as discussed above, 65 is a lightly doped region) abutting against the sidewall of the first concave (as seen in Fig. 13, 65 is abutting FC) and a highly doped region (80 is a highly doped region, “source/drain regions 80 may have an impurity (e.g., dopant) concentration in a range from about 1E19 cm−3 to about 1E21 cm−3”, col. 12, lines 18-20) abutting against the lightly doped region (as seen in Fig. 14A, 80 is abutting 65).
Regarding claim 13, Figs. 2-21B of Wang in combination with Figs. 1-15 of Mehandru disclose the transistor structure of claim 11, Figs. 2-21B of Wang further disclose wherein a location of the sidewall of the first concave is dependent on a thickness of the spacer layer on the sidewall of the gate region (as seen in Fig. 14A, the thickness of 73 is horizontally constrained by 80, “first gate spacers 72”, col. 11, line 3, and “gate 68”, col. 9, line 56, therefore in order to modify the thickness of 73 without changing the width of 80, 68 must be resized, and as 64 is the same width as 68, 64 must also be resized causing the location of the sidewall of FC to change, as the sidewall of FC is located on 64) and a thickness of the thermal oxide layer (as seen in Fig. 4, 52 is responsible for defining the shape of 64, thus the thickness of 52 in the horizontal direction will change the location of the sidewall of FC, as the sidewall of FC is located on 64).
Regarding claim 14, Figs. 2-21B of Wang in combination with Figs. 1-15 of Mehandru disclose the transistor structure of claim 11, Figs. 2-21B of Wang further disclose wherein a horizontal distance between an edge of the gate region and an edge of the first conductive region is dependent on a thickness of the spacer layer on the sidewall of the gate region (as seen in Figs.12 and 21B, “gate 68”, col. 9, line 56, is in the same location as 99A and 99B prior to the partial removal of 68, thus 68 is in the gate region, and as seen in Fig. 14A, the horizontal distance between the gate region represented by 68 and an edge of 80 is dependent on the thickness of 73 as 73 terminates at the same horizontal position as “first gate spacers 72”, col. 10, lines 66-67, and 80 directly abuts 72. Thus, 73 cannot be wider without also changing the position of 80, thus increasing the horizontal distance between an edge of 68 and an edge of 80) and a thickness of the thermal oxide layer (as seen in Fig. 4, 52 is responsible for defining the shape of 64, thus the thickness of 52 in the horizontal direction will affect the shape of 68 as the sidewalls of 68 are coplanar with the sidewalls of a portion of 64 as seen in Fig. 14A, thus changing the thickness of 52 in the correct horizontal direction will change the dimensions of 68 resulting in a change in the horizontal distance between 68 and 80).
Claims 15-19, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 10,497,577 B2, hereinafter “Wang”) in view of Kim et al. (US 10,147,650 B2, hereinafter “Kim”).
Regarding claim 15, Figs. 2-21B of Wang disclose a transistor structure (“FinFET device 100”, col. 2, line 37) comprising:
a substrate (“substrate 50”, col. 2, line 49) with a fin structure (“semiconductor fins 64 (e.g., 64A and 64B)”, col. 4, line 67, and col. 5, line 1);
an isolation wall (“capping layer 83”, col. 5, line 63, as seen in Fig. 12, 83 physically isolates 64 from “dielectric layer 85”, col. 8, lines 1-2, “top layer 87”, col. 7, line 63, and “insulation material 62”, col. 7, line 13) covering and surrounding sidewalls of the fin structure (as seen in Fig. 12, 83 covers and surrounds sidewalls of 64A and 64B) to fix the fin structure (as seen in Fig. 12, 83 buttresses the base of 64A and 64B, thereby adding structural rigidity and fixing 64A and 64B in place);
a shallow trench isolation (STI) region (together “recessed insulation material 62”, col. 9, line 23 and “first interlayer dielectric (ILD) 90”, col. 12, lines 23-24 form an STI region where “recessed insulation material 62 forms isolation regions 62, such as shallow trench isolation (STI) regions”, col. 9, lines 23-24, and as 90 is a dielectric material in a recess, seen in Fig. 21B, it can also be interpretated as an STI region) surrounding the fin structure (as seen in Fig. 21B, 62 surrounds 64A and 64B);
a gate region (together “gate dielectric 66 and gate 68”, col. 9, lines 55-56, form a gate region) above the fin structure (as seen in Fig. 13, 66 and 68 are above 64); and
a first conductive region (“source/drain regions 80”, col. 11, line 41, source/drain features are known in the art as conductive) abutting against the fin structure (as seen in Fig. 14A, 80 abuts 64), wherein the first conductive region comprises a first sidewall (“FSW” denoted in Fig. 14A is a first sidewall of 80), a second sidewall (“SSW” denoted in Fig. 14A is a second sidewall of 80) and a top wall (“TW” denoted in Fig. 14A is a top wall of 80), the second sidewall is connected to the fin structure (as seen in Fig. 14A, SSW is connected to 64 via “lightly doped drain (LDD) regions 65”, col. 10, lines 41-42), the first sidewall is opposite to the second sidewall (as seen in Fig. 14A, FSW is opposite SSW), and the first conductive region extends from the second sidewall to the first sidewall toward the STI region (Figs. 12 and 14A are cross-sectional figures perpendicular to one another, and 62 in Fig. 12 must extend into and out of the page or would otherwise be infinitesimally thin, therefore 80 extends from SSW to FSW towards 62 which extends parallel to 80 as seen in Fig. 14A).
Wang fails to disclose “wherein at least the first sidewall of the first conductive region connect to a metal region.”
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However, in a similar field of endeavor, Figs. 1-4 of Kim wherein at least the first sidewall of the first conductive region (“SW” is a first sidewall of “first epitaxial layer 120”, col. 10, line 8, that is equivalent to FSW of Wang) connect to a metal region (“metal contact 150”, col. 10, line 8, as seen in Fig. 2, at least SW is in contact with 150.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein at least the first sidewall of the first conductive region connect to a metal region” as taught by Kim in the system of Wang for the purpose of reducing “the contact resistance between the metal contact 150 and the first epitaxial layer 120”, col. 13, lines 27-28).
Regarding claim 16, Figs. 2-21B of Wang in combination with Figs. 1-4 of Kim disclose the transistor structure of claim 15, Figs. 1-4 of Kim further disclose wherein a top surface (hereinafter “TS”, shown in Fig. 2) and a sidewall of the first conductive region (hereinafter “SW”, shown in Fig. 2) are connected to the metal region (as seen in Fig. 2, TS and SW are connected to 150).
Regarding claim 17, Figs. 2-21B of Wang in combination with Figs. 1-4 of Kim disclose the transistor structure of claim 15, Figs. 1-4 of Kim further disclose wherein a top surface (hereinafter “TS”, shown in Fig. 2), a bottom surface (hereinafter “BS”, shown in Fig. 2) and a sidewall of the first conductive region (hereinafter “SW”, shown in Fig. 2) are connected to the metal region (as seen in Fig. 2, TS, BS, and SW are connected to 150).
Regarding claim 18, Figs. 2-21B of Wang in combination with Figs. 1-4 of Kim disclose the transistor structure of claim 15, Figs. 1-4 of Kim further disclose further comprising a shallow trench isolation region (“field insulating film 110”, col. 10, line 33) surrounding the fin structure (“first fin-type pattern F1”, col. 10, line 7, F1 of Kim is equivalent to 64 of Wang, as seen in Fig. 2, 110 is surrounding F1), wherein the first conductive region is also surrounded by the shallow trench isolation region (as seen in Fig. 2, the base of 120 is laterally surrounded by 110).
Regarding claim 19, Figs. 2-21B of Wang in combination with Figs. 1-4 of Kim disclose the transistor structure of claim 18, Figs. 1-4 of Kim further disclose wherein all of the first conductive region is surrounded by the shallow trench isolation region (as seen in Fig. 2, 110 is present on the left and right sides of 120, thus when viewed from above, all of 120 is surrounded by 110).
Regarding claim 22, Figs. 2-21B of Wang disclose the transistor structure of claim 20.
Wang fails to disclose “wherein at least two sides of the first conductive region connect to a metal region, and the isolation wall is configured to prevent the fin structure from collapsing.”
However, in a similar field of endeavor, Figs. 1-4 of Kim teach wherein at least two sides of the first conductive region (“first epitaxial layer 120”, col. 10, line 8, 120 of Kim is equivalent to 80 of Wang) connect to a metal region (“metal contact 150”, col. 10, line 8, as seen in Fig. 2, at least two sides of 120 connect to 150).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein at least two sides of the first conductive region connect to a metal region” as taught by Kim in the system of Wang for the purpose of “the contact resistance between the metal contact 150 and the first epitaxial layer 120” (col. 13, lines 27-28).
Regarding claim 23, Figs. 2-21B of Wang in disclose the transistor structure of claim 20.
Wang fails to disclose “further comprising a shallow trench isolation region surrounding the fin structure, wherein the first conductive region is also surrounded by the shallow trench isolation region.”
However, in a similar field of endeavor, Figs. 1-4 of Kim teach further comprising a shallow trench isolation region (“field insulating film 110”, col. 10, line 33) surrounding the fin structure (“first fin-type pattern F1”, col. 10, line 7, F1 of Kim is equivalent to 64 of Wang, as seen in Fig. 2, 110 is surrounding F1), wherein the first conductive region also surrounded by the shallow trench isolation region (as seen in Fig. 2, 110 is present on the left and right sides of “first epitaxial layer 120”, col. 10, line 8, where 120 of Kim is equivalent to 80 of Wang, thus when viewed from above, all of 120 is surrounded by 110).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising a shallow trench isolation region surrounding the fin structure, wherein the first conductive region is also surrounded by the shallow trench isolation region” as taught by Lim in the system of Wang for the purpose of electrically isolating the fin structure from neighboring devices.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 10,497,577 B2, hereinafter “Wang”) in view of Kim et al. (US 10,147,650 B2, hereinafter “Kim”) in view of Wu et al. (US 8,890,207 B2, hereinafter “Wu”).
Regarding claim 21, Figs. 2-21B of Wang in combination with Figs. 1-4 of Kim disclose the transistor structure of claim 18, Figs. 1-4 of Kim further disclose further comprising a shallow trench isolation region (110) surrounding the fin structure (110 is surrounding F1).
Wu in combination with Kim fails to disclose “wherein the bottom of the gate region over the shallow trench isolation region is lower the bottom of the first conductive region by more than 10nm.”
However, in a similar field of endeavor, Figs. 3A-11C of Wu teach wherein the bottom of the gate region over the shallow trench isolation region is lower the bottom of the first conductive region by more than 10nm (Wu does not directly disclose wherein the bottom of 170 as a part of the gate region is lower than the bottom of “heavily doped epitaxial layers 300/301” by more than 10 nm, where 300/301 of Wu are equivalent to 80 of Wang. However, Wu teaches “the fin may have a height 161 of between 7 nm and 50 nm”, col 3, lines 12-13, and “The source recess 270 and the drain recess 271 are formed with a depth 280 (see FIG. 9B) which may range from 0 nm to 150 nm”, col. 5, lines 43-45. Thus as 170 is deposited on the same surface from which 161 is measured, and as 280 is measured from a point above the top of 150, the bottom of 170 can be at least 50 nm below the bottom of 300/30 formed in 270/271, where 300/301 of Wu are equivalent to 80 of Wang. MPEP 2144.05 I states “In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.”)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the bottom of the gate region over the shallow trench isolation region is lower the bottom of the first conductive region by more than 10nm” as taught by Wu in the system of Wang in combination with Kim for the purpose of incorporating a margin of error into the etching process of the source/drain recess by allowing for a large window of etch depths.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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