Prosecution Insights
Last updated: April 19, 2026
Application No. 17/986,155

Magnetoresistive Random Access Memory Cell And Fabricating The Same

Final Rejection §103
Filed
Nov 14, 2022
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
3y 8m
To Grant
80%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
358 granted / 546 resolved
-2.4% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
40 currently pending
Career history
586
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§103
Attorney’s Docket Number: 2015-0435/24061.3167US03 Filing Date: 11/14/2022 Claimed Priority Date: 5/4/2020 (US 16/866,390) 9/18/2015 (US 14/858,054) Inventor: Hsu Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the amendment filed on 9/15/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis for a rejection as subjected to pre-AIA instead will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status The amendment filed on 9/15/2025 in reply to the Office action in paper no. 5, mailed on 6/17/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 9-11, 15, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Moriyama (US 2014/0197504) in view of Schwarz (US 6897532). Regarding 9, Moriyama (see, e.g., fig. 6) shows most aspects of the instant invention including a device comprising: A first electrode 32 on a substrate A free layer 40 on the first electrode A barrier layer 39 on the free layer, the barrier and free layers having the same width A pin layer 35 on the barrier layer An anti-ferromagnetic (AFM) layer on the pin layer (see, e.g., par. 0040), and A second electrode 42 on the AFM layer Regarding 16, Moriyama (see, e.g., fig. 6) shows most aspects of the instant invention including a device comprising: A first electrode 32 on a substrate A free layer 40 on the first electrode A barrier layer 39 on the free layer, the barrier and free layers having the same width A pin layer 35 on the barrier layer An anti-ferromagnetic (AFM) layer on the pin layer (see, e.g., par. 0040) A second electrode 42 on the AFM layer, and A third electrode 45 formed on and wider than the second electrode 42 Regarding claims 9 and 16, Moriyama fails to show that the barrier layer is wider than the pin layer, a first capping layer on a top surface of the barrier layer and interfacing with sidewalls of the pin layer, the AFM layer and the second electrode, and a second capping layer on a top surface of the first electrode and interfacing with sidewalls of the free layer and the barrier layer. Moriyama differently shows the pin 35 and barrier 39 layers having the same width. Schwarz teaches that devices having all layers with the same width are known in the art as equivalents to devices having the barrier layer wider than the pin layer (see, e.g., Schwarz: col.13/ll.21-37). Schwarz also suggests to one of ordinary skill in the art forming the first capping layer on a top surface of the barrier layer of Moriyama and interfacing with sidewalls of the pin layer, the AFM layer and the second electrode, and forming the second capping layer on a top surface of the first electrode and interfacing with sidewalls of the free layer and the barrier layer. He suggests doing so to use the capping layers to protect the other layers of the device (see, e.g., Schwarz: col.11/ll.35-42 and col.15/ll.33-42). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Moriyama’s barrier layer wider than the pin layer, and to include first and second capping layers in the device of Moriyama, as suggested by Schwarz, to protect the layers of the device. Regarding claim 10, Moriyama shows the AFM and pin 35 layers having the same widths (see, e.g., fig. 6 and par. 0040). Regarding claim 11, Moriyama shows the device further comprising a third electrode 45 interfacing with the second electrode 42, wherein the second electrode and the AFM layer have the same widths, and the third electrode 45 is wider than the second electrode 42 (see, e.g., fig. 8 and par. 0040). Regarding claim 15, Schwarz (see, e.g., fig. 8) suggests the barrier layer 32 has a top surface facing away from the substrate 22, and the first capping layer 42 interfaces with the top surface of the barrier layer. Regarding claim 20, Schwarz (see, e.g., fig. 8) suggests the second capping layer 50 physically contacts the first electrode layer 24, and the barrier 32 and free layers be positioned between the first capping layer 42 and the first electrode 24 thereby preventing the first capping layer from physically contacting the first electrode. Allowable Subject Matter Claims 1-8 are allowed. Claims 12-14 and 17-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims. Response to Arguments The applicant argues: Moriyama/Schwarz fail to show a first capping layer on a top surface of the barrier layer and interfacing with sidewalls of the pin layer, the AFM layer and the second electrode. The examiner responds: Moriyama does fail to show a first capping layer on a top surface of the barrier layer interfacing with sidewalls of the pin layer, the AFM layer and the second electrode. Schwarz, on the other hand, suggests to one of ordinary skill in the art forming a first capping layer 42 on a top surface of the barrier layer of Moriyama interfacing with sidewalls of the pin layer, the AFM layer and the second electrode. He suggests doing so to use the capping layer to protect the other layers of the device (see, e.g., Schwarz: col.11/ll.35-42 and col.15/ll.33-42). Conclusion Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action. Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/ Primary Examiner, Art Unit 2814 MDP/mdp February 23, 2026
Read full office action

Prosecution Timeline

Nov 14, 2022
Application Filed
Jun 14, 2025
Non-Final Rejection — §103
Sep 15, 2025
Response Filed
Feb 23, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12568612
Arrays Of Capacitors, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming An Array Of Capacitors
2y 5m to grant Granted Mar 03, 2026
Patent 12557215
SEMICONDUCTOR PACKAGE USING FLIP-CHIP TECHNOLOGY
2y 5m to grant Granted Feb 17, 2026
Patent 12557710
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Feb 17, 2026
Patent 12541113
IMAGE SENSOR INCLUDING COLOR SEPARATING LENS ARRAY AND ELECTRONIC DEVICE INCLUDING THE IMAGE SENSOR
2y 5m to grant Granted Feb 03, 2026
Patent 12543370
THIN-FILM TRANSISTOR ARRAY SUBSTRATE WITH CONNECTION NODE AND DISPLAY DEVICE INCLUDING THE SAME
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
80%
With Interview (+14.8%)
3y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month