DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/14/2022, 01/12/2023, and 01/13/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species A, Figs. 7-11, and Claims 1-13 in the reply filed on 10/13/2025 is acknowledged. Claims 14 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/13/2025.
Drawings
The drawings are objected to because FIG. 3G mentioned in specification [0153] is missing in the drawings. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Examiner has found the following informalities, but may not be an exhaustive list. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
[00145] on page 27 recites “third scan signal Gii”; it should read “third scan signal Gli”.
[00149] on page 28 recites “thus he sixth and seventh transistors”; it should read “thus the sixth and seventh transistors”.
[00184] on page 34 recites “sixth sub-semiconductor pattern ACT_T2”; it should read , “sixth sub-semiconductor pattern ACT_T6”.
[00186] on page 35 recites “gate electrode of the eighth transistors T8”; it should read “gate electrode of the eighth transistor T8”.
[00207] on page 38 recites “third sub-semiconductor region ACT3_T3”; it should read “third sub-semiconductor region ACT_T3”.
[00212] on page 39 recites “fifth transistor T2”; it should read “fifth transistor T5”.
[00234] on page 44 recites “polyimides rein”; it should read “polyimides resin”.
[00276] and [0295] on pages 54 and 58 respectively recites “nitrogen oxide (SiNx)”; this phrase needs correction.
[00291] on page 57 recites “Referring to FIGS. 12 to 10A”; this phrase needs correction.
[00294] on page 58 recites “first transistor group TR_R1 and the second transistor group TR_R2”; it should read “first transistor group TR_G1 and the second transistor group TR_G2”.
[00294] on page 58 recites “thickness d0 of the barrier layer BRL” and [00295] recites “thickness d0 of the first buffer layer BFL1”; this phrase needs to be corrected to designate one reference number per each part.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Moon et al. (KR20200045598A; hereinafter Moon).
Regarding Claim 1, Moon discloses a display device [0036] comprising:
a substrate (110, FIG. 1 reproduced below, [0040]);
a buffer layer on the substrate (120, FIG. 1, [0041]);
a driving transistor (TRb) on the buffer layer (122, FIG. 1, [0043]) and including a first semiconductor pattern (130b), a first gate electrode (150b), a first source electrode (173b), and a first drain electrode (175b), FIG. 1, [0045]; and
a switching transistor (TRa) on the buffer layer (122 and 121, FIG. 1, [0043]) and spaced apart from the driving transistor (TRb), the switching transistor (TRa) including a second semiconductor pattern (130a), a second gate electrode (150a), a second source electrode (173a), and a second drain electrode (175a), FIG. 1, [0045],
wherein the buffer layer (120) includes a first buffer layer (121) including silicon nitride (first buffer layer 121 including silicon nitride (SiNx), [0044]) and a second buffer layer including silicon oxide (second buffer layer 122 may include silicon oxide (SiOx), [0043]),
only the second buffer layer (122) is under the first semiconductor pattern (130b) of the driving transistor (TRb), FIG. 1, [0054], and
the first buffer layer (121) and the second buffer layer (122) are under the second semiconductor pattern (130a) of the switching transistor (TRa), FIG. 1, [0051].
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Moon: FIG. 1
Regarding Claim 3, Moon discloses the display device of claim 1, wherein a hydrogen ion concentration included in the second semiconductor pattern (130a) is greater than a hydrogen ion concentration included in the first semiconductor pattern (130b), FIG. 1, [0032]. Moon [0032] discloses that charge mobility of the semiconductor layer 130a may be increased by hydrogen supplied from layer 121 including Silicon Nitride; and hydrogen is not supplied to the layer 130b, indicating a hydrogen ion concentration included in the second semiconductor pattern (130a) is greater than a hydrogen ion concentration included in the first semiconductor pattern (130b).
Regarding Claim 6, Moon discloses the display device of claim 1, wherein a first thickness of the second buffer layer under the first semiconductor pattern (thickness of 122 under 130b) is equal to a sum of a second thickness of the second buffer layer under the second semiconductor pattern (thickness of 122 under 130a) and a third thickness of the first buffer layer under the second semiconductor pattern (thickness of 121 under 130a), FIG. 1, [0041], [0043]. Moon [0041] discloses that the buffer layer 120 may provide a flat surface on the substrate 110; and [0043] discloses the upper surfaces of the second buffer layer 122 in regions 1A and 2A may be flat and buffer layers 121 and 122 are formed under the first semiconductor pattern 130a and only buffer layer 122 is formed under 130b, indicating a first thickness of the second buffer layer under the first semiconductor pattern is equal to a sum of a second thickness of the second buffer layer under the second semiconductor pattern and a third thickness of the first buffer layer under the second semiconductor pattern.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Zhang (US20190043426A1; hereinafter Zhang).
Regarding Claim 9, Moon discloses the display device of claim 1, wherein a plurality of pixels are on the substrate (pixel unit PP with pixels PX on the substrate 110, FIG. 11, [109], [0122]), and each of the pixels includes:
a light emitting element (pixel PX includes organic light emitting diode (OLED), [0113]);
the driving transistor (Qd) connected between a first power supply (a driving voltage line PL transferring a driving voltage ELVDD, [0114]) and a second node (node connecting output of Qd and OLED) and configured to control a driving current (Id) supplied to the light emitting element (OLED) in response to a voltage of a first node (node between Qs and gate of Qd) connected to the first gate electrode (Control gate electrode of Qd), FIG. 10 reproduced below, [0117];
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Moon: FIG. 10
Moon does not disclose “a first capacitor including a first electrode connected to the first node and a second electrode connected to a third node; a second transistor connected between the third node and a data line and configured to be turned on by a first scan signal; a third transistor connected between the first node and the second node and configured to be turned on by a second scan signal; a fourth transistor connected between the first node and an initialization power supply and configured to be turned on by a third scan signal; and a fifth transistor connected between a reference power supply and the third node and configured to be turned on by the second scan signal.”
In a similar device, Zhang discloses a pixel circuit, a display panel, and a driving method [0002].
Zhang discloses: the driving transistor (driving sub-circuit M1) connected between a first power supply (high voltage input terminal DD) and a second node (M1’s output node feeding light emission control transistor M7) and configured to control a driving current (driving current I) supplied to the light emitting element (light-emitting sub-circuit 400) in response to a voltage of a first node (gate of driving sub-circuit M1) connected to the first gate electrode (gate electrode of M1), FIG. 2 reproduced below, [0046];
a first capacitor (C2) including a first electrode connected to the first node (gate of driving sub-circuit M1) and a second electrode connected to a third node (node between C1 and C2), FIG. 2, [0060];
a second transistor (data writing transistor M4) connected between the third node (node between C1 and C2) and a data line (DATA) and configured to be turned on by a first scan signal (data writing control gate line G(N)), FIG. 2, [0104], [0110];
a third transistor (second compensation transistor M3) connected between the first node (gate of M1) and the second node (node between M1 and M7) and configured to be turned on by a second scan signal (compensation control gate line G(N-1)), FIG. 2, [0108];
a fourth transistor (first initialization transistor M5) connected between the first node (gate of M1) and an initialization power supply (reference voltage input terminal REF) and configured to be turned on by a third scan signal (initialization control gate line G(N-2)), FIG. 2, [0107]; and
a fifth transistor (first compensation transistor M2) connected between a reference power supply (REF) and the third node (node between C1 and C2), and configured to be turned on by the second scan signal (compensation control gate line G(N-1)), FIG. 2, [0108].
Zhang discloses that a display device as taught improves the uniformity of the display brightness and the image quality [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Zhang’s disclosure to Moon’s display to improve uniformity of the display brightness and the image quality as disclosed by Zhang [0047].
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Regarding Claim 11, The combination of Moon and Zhang disclose the display device of claim 9.
Zhang further discloses: wherein the switching transistor includes the second transistor (M4, [0104]), the third transistor (M3, [0103]), the fourth transistor (M5, [0102]), and the fifth transistor (M2, [103]), FIG. 2.
Zhang discloses that a display device as taught improves the uniformity of the display brightness and the image quality [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Zhang’s disclosure to Moon’s display to improve uniformity of the display brightness and the image quality as disclosed by Zhang [0047].
Regarding Claim 13, The combination of Moon and Zhang disclose the display device of claim 9.
Zhang further discloses: further comprising a second capacitor (data voltage storage capacitor C1) including a first electrode connected to the first power supply (high voltage signal input terminal DD) and a second electrode connected to the third node (node between C1 and C2), FIG. 2, [0054].
Zhang discloses that a display device as taught improves the uniformity of the display brightness and the image quality [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Zhang’s disclosure to Moon’s display to improve uniformity of the display brightness and the image quality as disclosed by Zhang [0047].
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Hiromasu et al. (US20170287946A1; hereinafter Hiromasu).
Regarding Claim 4, Moon discloses the display device of claim 1.
Moon does not disclose “wherein a first thickness of the second buffer layer under the first semiconductor pattern is equal to a second thickness of the second buffer layer under the second semiconductor pattern.”
In a similar art, Hiromasu discloses a display device [0052]: wherein a first thickness of the second buffer layer (thickness T12 of layer 12 made of SiO2) under the first semiconductor pattern (13A) is equal to a second thickness of the second buffer layer (thickness T12 of layer 12 made of SiO2) under the second semiconductor pattern (13B), FIG. 14, (a silicon oxide layer having a layer thickness T12 of approximately 200 nm, [0126]).
Hiromasu discloses that a device as taught reduces the leak current and the electricity consumption of the display [0241]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s display device to reduce the leak current and the electricity consumption as disclosed by Hiromasu [0241].
Regarding Claim 5, The combination of Moon and Hiromasu disclose the display device of claim 4.
Hiromasu further discloses: wherein a third thickness of the first buffer layer (thickness T11B of layer 11 made of Silicon Nitride, approximately 100nm [0057], [0124]) under the second semiconductor pattern (13B) is less than the second thickness (T12 = 200nm, [0126]), FIG. 14.
Hiromasu discloses that a device as taught reduces the leak current and the electricity consumption of the display [0241]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s display device to reduce the leak current and the electricity consumption as disclosed by Hiromasu [0241].
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Kim et al. (US20200395427A1; hereinafter Kim).
Regarding Claim 7, Moon discloses the display device of claim 1.
Moon does not disclose “further comprising a barrier layer including silicon oxide between the substrate and the buffer layer.”
In a similar art, Kim discloses a display device [0006].
Kim discloses: further comprising a barrier layer (140) including silicon oxide (the multi-buffer layer 140 is formed in a manner such that silicon nitride (SiNx) and silicon oxide (SiOx) are alternately stacked, [0049]) between the substrate (101) and the buffer layer (112), FIG. 7, [0049].
Kim discloses that a device as taught comprising a barrier layer impedes the diffusion of moisture and/or oxygen that has permeated the substrate and improves the reliability of the display device [0049]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s device to improve the reliability of the display device as disclosed by Kim [0049].
Regarding Claim 8, The combination of Moon and Kim disclose the display device of claim 7.
Kim further discloses: wherein the first buffer layer (the lower buffer layer 112 may be formed of a Si, silicon nitride, silicon oxide, or the like, [0049]) is on the barrier layer (140), and the second buffer layer is on the first buffer layer (the upper buffer layer 122 are formed of silicon oxide, [0057]), FIG. 7, [0092], [0096].
Kim discloses that a device as taught comprising a barrier layer impedes the diffusion of moisture and/or oxygen that has permeated the substrate and improves the reliability of the display device [0049]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s device to improve the reliability of the display device as disclosed by Kim [0049].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Jong et al. (KR20050035806A; hereinafter Jong).
Regarding Claim 2, Moon discloses the display device of claim 1.
Moon does not disclose “wherein the first semiconductor pattern and the second semiconductor pattern include polysilicon.”
In a similar art, Jong discloses a flat panel display device [page 2, para 1].
Jong discloses wherein the first semiconductor pattern (130a) and the second semiconductor pattern (130b) include polysilicon (active layer 130a, 130b is made of polycrystalline silicon, page 4, para 1, FIG. 1b).
Jong discloses that a device as taught provides a display device with improved resolution [page 2, para 1]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s device including polysilicon semiconductor patterns in order to provide a display device with improved resolution as disclosed by Jong [page 2, para 1].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Zhang further in view of Sung et al. (US20190378887A1; hereinafter Sung).
Regarding Claim 10, The combination of Moon and Zhang disclose the display device of claim 9.
The combination of Moon and Zhang does not disclose: “wherein the second transistor includes a (2_1)th transistor and a (2_2)th transistor connected in series,
the third transistor includes a (3_1)th transistor and a (3_2)th transistor connected in series, the fourth transistor includes a (4_1 )th transistor and a (4_2)th transistor connected in series, and the fifth transistor includes a (5_1 )th transistor and a (5_2)th transistor connected in series.”
In a similar art, Sung discloses an organic light emitting diode display [0002].
The combination of Zhang and Sung discloses:
the third transistor (Zhang: M3, FIG. 2, [108]) includes a (3_1)th transistor and a (3_2)th transistor connected in series, the fourth transistor (Zhang: M5, FIG. 2, [107]) includes a (4_1)th transistor and a (4_2)th transistor connected in series (Sung: FIG. 19, [0023]). Sung [0023] discloses the pixel may further include a (3-1)th transistor and a (3-2)th transistor that are connected in series, and a (4-1)th transistor and a (4-2)th transistor that are connected in series.
wherein the second transistor (Zhang: M4, FIG. 2, [104]) includes a (2_1)th transistor and a (2_2)th transistor connected in series, and the fifth transistor (Zhang: M2, FIG. 2, [108]) includes a (5_1)th transistor and a (5_2)th transistor connected in series. Sung [0058] discloses the pixel in the display includes multiple transistors connected in series, indicating the second transistor can include (2-1)th and (2-2)th transistors in series and the fifth transistor can include (5-1)th and (5-2)th transistors in series.
Sung discloses that a device as taught prevents current leakage and provides a display device with high-quality characteristics such as low power consumption, high luminance, and high response speed [0003], [0092]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Moon and Zhang’s device to include the serially connected structure to prevent current leakage and provide a display device with low power consumption, high luminance, and high response speed as disclosed by Sung [0003], [0092].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Zhang further in view of Lin et al. (US20200226978A1; hereinafter Lin).
Regarding Claim 12, The combination of Moon and Zhang disclose the display device of claim 9.
The combination of Moon and Zhang does not disclose “further comprising:
a sixth transistor connected between the first power supply and a fifth node connected to one electrode of the driving transistor and configured to be turned on by a first emission control signal; a seventh transistor connected between the second node and a fourth node and configured to be turned on by a second emission control signal;
an eighth transistor connected between the fourth node and an anode initialization power supply and configured to be turned on by a fourth scan signal; and a ninth transistor connected between the fifth node and a bias power supply and configured to be turned on by the fourth scan signal.”
In a similar art, Lin discloses display driver circuitry for displays [0002].
Lin discloses: further comprising:
a sixth transistor (Tem1) connected between the first power supply (VDDEL) and a fifth node (Node 1) connected to one electrode of the driving transistor (Tdrive) and configured to be turned on by a first emission control signal (EM(n)), FIG. 3, [0061];
a seventh transistor (Tem2) connected between the second node (Node 3) and a fourth node (Node 4) and configured to be turned on by a second emission control signal (EM(n)), FIG. 3, [0062];
an eighth transistor (Tar) connected between the fourth node (Node 4) and an anode initialization power supply (Var) and configured to be turned on by a fourth scan signal (SC3(n+1)), FIG. 10, [0088]; and
a ninth transistor (Tobs) connected between the fifth node (Node 1) and a bias power supply (Vobs) and configured to be turned on by the fourth scan signal (SC3), FIG. 17, [0110].
Lin discloses that a device as taught helps mitigate hysteresis and improve first frame response of the display [0071]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Moon and Zhang’s device to help mitigate hysteresis and improve first frame response as disclosed by Lin [0071].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KRISHNA J PALANISWAMY/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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