DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/11/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s amendments to claim 1 has been fully considered. Based on the cited prior arts Moon, Zhang, Hiromasu, Kim, Jong, Sung, and Lin and new grounds of rejection from Gu (US20200411624A1) the claims 1-13 are rejected.
Response to Amendment
Applicant’s amendments with respect to the drawing objection has been fully considered and resolve the drawing objections. The drawing objection has been withdrawn. Applicant’s amendments with respect to the specification objection has been fully considered and resolve the specification objection. The specification objection has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Gu (US20200411624A1; hereinafter Gu) in view of Jong et al. (KR20050035806A; hereinafter Jong).
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Regarding Claim 1 (Currently amended), Gu discloses a display device [0037] comprising:
a substrate (base substrate 10), FIG. 2, [0044];
a buffer layer on the substrate (first buffer layer 20 and second buffer layer 40), FIG. 2, [0046];
a driving transistor (TFTs A are driving TFTs, [0049]) on the buffer layer (20 and 40) and including a first semiconductor pattern (active layer 51), a first gate electrode (a gate 71), a first source electrode (source 91), and a first drain electrode (drain 92), FIG. 4 reproduced above, [0061]; and
a switching transistor (TFTs B are switching TFTs, [0049]) on the buffer layer (20 and 40) and spaced apart from the driving transistor (FIG. 1, [0038]), the switching transistor (TFTs B) including a second semiconductor pattern (active layer 51), a second gate electrode (gate 71), a second source electrode (source 91), and a second drain electrode (drain 92), FIG. 4, [0061];
wherein the driving transistor (TFTs A) and the switching transistor (TFTs B) are included in each of a plurality of pixels, FIG. 1, [0038], [0039], [0040]. Gu discloses the pixel circuit in the display device is a 2T1C circuit which includes two TFTs (M1 and M2) and one capacitor; and M1 is a driving transistor and M2 is a switching transistor, indicating the driving transistor and the switching transistors are included in each of a plurality of pixels.
Gu [0057] discloses buffer layers 20 and 40 may include silicon dioxide, but does not disclose “wherein the buffer layer includes a first buffer layer including silicon nitride and a second buffer layer including silicon oxide, only the second buffer layer is under the first semiconductor pattern of the driving transistor, and the first buffer layer and the second buffer layer are under the second semiconductor pattern of the switching transistor.”
In a similar art, Jong discloses a flat panel display device [page 2, para 1].
Jong discloses: wherein the buffer layer includes a first buffer layer including silicon nitride (110 is a silicon nitride film, page 4, para 15) and a second buffer layer including silicon oxide (120 is silicon oxide, page 4, para 10 and page 5, para 18), FIGS. 1A-1C.
Jong [page 5, para 18, FIG. 1D reproduced above] discloses the second buffer layer 120 is formed on the entire surface of the insulating substrate 100 including the active layers 130a and 130b on the circuit portion A and the pixel portion B, and Jong [page 5, para 16] discloses first buffer layer 110 remains only in circuit portion A under active layer 130a. Jong [page 6, para 22] discloses a thin film transistor is formed in each of the circuit portion A and the pixel portion B.
The combination of Gu and Jong discloses only the second buffer layer (Jong:120) is under the first semiconductor pattern of the driving transistor (Gu: active layer 51 under TFTA), and
The combination of Gu and Jong discloses the first buffer layer (110) and the second buffer layer (120) are under the second semiconductor pattern of the switching transistor (Gu: active layer 51 under TFTB).
Jong discloses that a device as taught using transistors having different electrical characteristics can improve the electrical characteristics and performance of the display device [page 4, para 7]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu’s display device to improve the electrical characteristics and improve the device performance as disclosed by Jong [page 4, para 7].
Regarding Claim 2, The combination of Gu and Jong discloses the display device of claim 1.
Gu does not disclose “wherein the first semiconductor pattern and the second semiconductor pattern include polysilicon.”
Jong discloses wherein the first semiconductor pattern (130b) and the second semiconductor pattern (130a) include polysilicon (active layer 130a, 130b is made of polycrystalline silicon, page 5, para 17).
Jong discloses that a device as taught provides a display device with improved resolution [page 3, para 3]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu’s device including polysilicon semiconductor patterns in order to provide a display device with improved resolution as disclosed by Jong [page 3, para 3].
Regarding Claim 3, The combination of Gu and Jong discloses the display device of claim 1.
Gu does not disclose “wherein a hydrogen ion concentration included in the second semiconductor pattern is greater than a hydrogen ion concentration included in the first semiconductor pattern.”
Jong discloses: wherein a hydrogen ion concentration included in the second semiconductor pattern (130a) is greater than a hydrogen ion concentration included in the first semiconductor pattern (130b), FIG. 1d, [page 6, para 25].
Jong discloses the heat treatment facilitates the diffusion of hydrogen from the first buffer layer 110 into the active layers 130a, indicating the hydrogen ion concentration in second semiconductor pattern 130a is greater than that of the first semiconductor pattern 130b.
Jong discloses that a device as taught can improve the electrical characteristics and performance of the display device [page 4, para 7]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu’s display device to improve the electrical characteristics and improve the device performance as disclosed by Jong [page 4, para 7].
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Gu and Jong in view of Hiromasu et al. (US20170287946A1; hereinafter Hiromasu).
Regarding Claim 4, The combination of Gu and Jong discloses the display device of claim 1.
The combination of Gu and Jong does not disclose “wherein a first thickness of the second buffer layer under the first semiconductor pattern is equal to a second thickness of the second buffer layer under the second semiconductor pattern.”
In a similar art, Hiromasu discloses a display device [0052].
Hiromasu discloses: wherein a first thickness of the second buffer layer (thickness T12 of layer 12 made of SiO2) under the first semiconductor pattern (13A) is equal to a second thickness of the second buffer layer (thickness T12 of layer 12 made of SiO2) under the second semiconductor pattern (13B), FIG. 14, (a silicon oxide layer having a layer thickness T12 of approximately 200 nm, [0126]).
Hiromasu discloses that a device as taught reduces the leak current and the electricity consumption of the display [0241]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu and Jong’s display device to reduce the leak current and the electricity consumption as disclosed by Hiromasu [0241].
Regarding Claim 5, The combination of Gu, Jong, and Hiromasu discloses the display device of claim 4.
Hiromasu further discloses: wherein a third thickness of the first buffer layer (thickness T11B of layer 11 made of Silicon Nitride, approximately 100nm [0057], [0124]) under the second semiconductor pattern (13B) is less than the second thickness (T12 = 200nm, [0126]), FIG. 14.
Hiromasu discloses that a device as taught reduces the leak current and the electricity consumption of the display [0241]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the display device to reduce the leak current and the electricity consumption as disclosed by Hiromasu [0241].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gu and Jong in view of Moon et al. (KR20200045598A; hereinafter Moon).
Regarding Claim 6, The combination of Gu and Jong discloses the display device of claim 1.
The combination of Gu and Jong does not disclose “wherein a first thickness of the second buffer layer under the first semiconductor pattern is equal to a sum of a second thickness of the second buffer layer under the second semiconductor pattern and a third thickness of the first buffer layer under the second semiconductor pattern.”
In a similar art, Moon discloses a display device [0001].
Moon discloses: wherein a first thickness of the second buffer layer under the first semiconductor pattern (thickness of 122 under 130b) is equal to a sum of a second thickness of the second buffer layer under the second semiconductor pattern (thickness of 122 under 130a) and a third thickness of the first buffer layer under the second semiconductor pattern (thickness of 121 under 130a), FIG. 1, [0041], [0043].
Moon [0041] discloses that the buffer layer 120 may provide a flat surface on the substrate 110; and [0043] discloses the upper surfaces of the second buffer layer 122 in regions 1A and 2A may be flat and buffer layers 121 and 122 are formed under the first semiconductor pattern 130a and only buffer layer 122 is formed under 130b, indicating a first thickness of the second buffer layer under the first semiconductor pattern is equal to a sum of a second thickness of the second buffer layer under the second semiconductor pattern and a third thickness of the first buffer layer under the second semiconductor pattern.
Moon discloses that a device as taught enables implementation of a high resolution display device [0033]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu and Jong’s display device to implement a high resolution display device as disclosed by Moon [0033].
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Jong, further in view of Kim et al. (US20200395427A1; hereinafter Kim).
Regarding Claim 7, The combination of Gu and Jong discloses the display device of claim 1.
The combination of Gu and Jong does not explicitly disclose “further comprising a barrier layer including silicon oxide between the substrate and the buffer layer.”
In a similar art, Kim discloses a display device [0006].
Kim discloses: further comprising a barrier layer (140) including silicon oxide (the multi-buffer layer 140 is formed in a manner such that silicon nitride (SiNx) and silicon oxide (SiOx) are alternately stacked, [0049]) between the substrate (101) and the buffer layer (112), FIG. 7, [0049].
Kim discloses that a device as taught comprising a barrier layer impedes the diffusion of moisture and/or oxygen that has permeated the substrate and improves the reliability of the display device [0049]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu and Jong’s device to improve the reliability of the display device as disclosed by Kim [0049].
Regarding Claim 8, The combination of Gu, Jong, and Kim disclose the display device of claim 7.
Kim further discloses: wherein the first buffer layer (the lower buffer layer 112 may be formed of a Si, silicon nitride, silicon oxide, or the like, [0049]) is on the barrier layer (140), and the second buffer layer is on the first buffer layer (the upper buffer layer 122 are formed of silicon oxide, [0057]), FIG. 7, [0092], [0096].
Kim discloses that a device as taught comprising a barrier layer impedes the diffusion of moisture and/or oxygen that has permeated the substrate and improves the reliability of the display device [0049]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device to improve the reliability of the display device as disclosed by Kim [0049].
Claims 9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Jong, further in view of Zhang (US20190043426A1; hereinafter Zhang).
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Regarding Claim 9, The combination of Gu and Jong discloses the display device of claim 1.
Gu discloses: wherein a plurality of pixels are on the substrate (sub-pixels on substrate 10, FIG. 2, [0040], [0044]), and each of the pixels includes:
a light emitting element (organic light emitting diode (OLED)), [0038];
the driving transistor (M1) connected between a first power supply (ELVDD) and a second node (node between M1 and OLED) and configured to control a driving current (M1 converts a stored voltage into a current) supplied to the light emitting element (OLED) in response to a voltage of a first node (Vdata applied to gate node of M1 via data line DL) connected to the first gate electrode (gate electrode of M1), FIG. 1 reproduced above, [0039].
The combination of Gu and Jong does not disclose “a first capacitor including a first electrode connected to the first node and a second electrode connected to a third node; a second transistor connected between the third node and a data line and configured to be turned on by a first scan signal; a third transistor connected between the first node and the second node and configured to be turned on by a second scan signal; a fourth transistor connected between the first node and an initialization power supply and configured to be turned on by a third scan signal; and a fifth transistor connected between a reference power supply and the third node and configured to be turned on by the second scan signal.”
In a similar device, Zhang discloses a pixel circuit, a display panel, and a driving method [0002].
Zhang discloses: the driving transistor (driving sub-circuit M1) connected between a first power supply (high voltage input terminal DD) and a second node (M1’s output node feeding light emission control transistor M7) and configured to control a driving current (driving current I) supplied to the light emitting element (light-emitting sub-circuit 400) in response to a voltage of a first node (gate of driving sub-circuit M1) connected to the first gate electrode (gate electrode of M1), FIG. 2 reproduced above, [0046];
a first capacitor (C2) including a first electrode connected to the first node (gate of driving sub-circuit M1) and a second electrode connected to a third node (node between C1 and C2), FIG. 2, [0060];
a second transistor (data writing transistor M4) connected between the third node (node between C1 and C2) and a data line (DATA) and configured to be turned on by a first scan signal (data writing control gate line G(N)), FIG. 2, [0104], [0110];
a third transistor (second compensation transistor M3) connected between the first node (gate of M1) and the second node (node between M1 and M7) and configured to be turned on by a second scan signal (compensation control gate line G(N-1)), FIG. 2, [0108];
a fourth transistor (first initialization transistor M5) connected between the first node (gate of M1) and an initialization power supply (reference voltage input terminal REF) and configured to be turned on by a third scan signal (initialization control gate line G(N-2)), FIG. 2, [0107]; and
a fifth transistor (first compensation transistor M2) connected between a reference power supply (REF) and the third node (node between C1 and C2), and configured to be turned on by the second scan signal (compensation control gate line G(N-1)), FIG. 2, [0108].
Zhang discloses that a display device as taught improves the uniformity of the display brightness and the image quality [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu and Jong’s display to improve uniformity of the display brightness and the image quality as disclosed by Zhang [0047].
Regarding Claim 11, The combination of Gu, Jong, and Zhang discloses the display device of claim 9.
Zhang further discloses: wherein the switching transistor includes the second transistor (M4, [0104]), the third transistor (M3, [0103]), the fourth transistor (M5, [0102]), and the fifth transistor (M2, [103]), FIG. 2.
Zhang discloses that a display device as taught improves the uniformity of the display brightness and the image quality [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the display to improve uniformity of the display brightness and the image quality as disclosed by Zhang [0047].
Regarding Claim 13, The combination of Gu, Jong, and Zhang discloses the display device of claim 9.
Zhang further discloses: further comprising a second capacitor (data voltage storage capacitor C1) including a first electrode connected to the first power supply (high voltage signal input terminal DD) and a second electrode connected to the third node (node between C1 and C2), FIG. 2, [0054].
Zhang discloses that a display device as taught improves the uniformity of the display brightness and the image quality [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the display to improve uniformity of the display brightness and the image quality as disclosed by Zhang [0047].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Jong, further in view of Zhang, still further in view of Sung et al. (US20190378887A1; hereinafter Sung).
Regarding Claim 10, The combination of Gu, Jong, and Zhang discloses the display device of claim 9.
The combination of Gu, Jong, and Zhang does not disclose: “wherein the second transistor includes a (2_1)th transistor and a (2_2)th transistor connected in series,
the third transistor includes a (3_1)th transistor and a (3_2)th transistor connected in series, the fourth transistor includes a (4_1 )th transistor and a (4_2)th transistor connected in series, and the fifth transistor includes a (5_1 )th transistor and a (5_2)th transistor connected in series.”
In a similar art, Sung discloses an organic light emitting diode display [0002].
The combination of Zhang and Sung discloses:
the third transistor (Zhang: M3, FIG. 2, [108]) includes a (3_1)th transistor and a (3_2)th transistor connected in series, the fourth transistor (Zhang: M5, FIG. 2, [107]) includes a (4_1)th transistor and a (4_2)th transistor connected in series (Sung: FIG. 19, [0023]). Sung [0023] discloses the pixel may further include a (3-1)th transistor and a (3-2)th transistor that are connected in series, and a (4-1)th transistor and a (4-2)th transistor that are connected in series.
wherein the second transistor (Zhang: M4, FIG. 2, [104]) includes a (2_1)th transistor and a (2_2)th transistor connected in series, and the fifth transistor (Zhang: M2, FIG. 2, [108]) includes a (5_1)th transistor and a (5_2)th transistor connected in series. Sung [0058] discloses the pixel in the display includes multiple transistors connected in series, indicating the second transistor can include (2-1)th and (2-2)th transistors in series and the fifth transistor can include (5-1)th and (5-2)th transistors in series.
Sung discloses that a device as taught prevents current leakage and provides a display device with high-quality characteristics such as low power consumption, high luminance, and high response speed [0003], [0092]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu, Jong, and Zhang’s device to include the serially connected structure to prevent current leakage and provide a display device with low power consumption, high luminance, and high response speed as disclosed by Sung [0003], [0092].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Jong, further in view of Zhang, still further in view of Lin et al. (US20200226978A1; hereinafter Lin).
Regarding Claim 12, The combination of Gu, Jong, and Zhang discloses the display device of claim 9.
The combination of Gu, Jong, and Zhang does not disclose “further comprising:
a sixth transistor connected between the first power supply and a fifth node connected to one electrode of the driving transistor and configured to be turned on by a first emission control signal; a seventh transistor connected between the second node and a fourth node and configured to be turned on by a second emission control signal;
an eighth transistor connected between the fourth node and an anode initialization power supply and configured to be turned on by a fourth scan signal; and a ninth transistor connected between the fifth node and a bias power supply and configured to be turned on by the fourth scan signal.”
In a similar art, Lin discloses display driver circuitry for displays [0002].
Lin discloses: further comprising:
a sixth transistor (Tem1) connected between the first power supply (VDDEL) and a fifth node (Node 1) connected to one electrode of the driving transistor (Tdrive) and configured to be turned on by a first emission control signal (EM(n)), FIG. 3, [0061];
a seventh transistor (Tem2) connected between the second node (Node 3) and a fourth node (Node 4) and configured to be turned on by a second emission control signal (EM(n)), FIG. 3, [0062];
an eighth transistor (Tar) connected between the fourth node (Node 4) and an anode initialization power supply (Var) and configured to be turned on by a fourth scan signal (SC3(n+1)), FIG. 10, [0088]; and
a ninth transistor (Tobs) connected between the fifth node (Node 1) and a bias power supply (Vobs) and configured to be turned on by the fourth scan signal (SC3), FIG. 17, [0110].
Lin discloses that a device as taught helps mitigate hysteresis and improve first frame response of the display [0071]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Gu, Jong, and Zhang’s device to help mitigate hysteresis and improve first frame response as disclosed by Lin [0071].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
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