DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-14, in the reply filed on March 2, 2026, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 15-20, are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-10, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U. S. Patent Application Publication No. 2010/0130016 (hereinafter referred to as DeVilliers ‘016).
DeVilliers ‘016, in the abstract, and in [0027]-[0033], discloses a process of forming patterns in the substrate the substrate includes target layer wherein the target layer (multiple layers of metal layer, semiconductor layer, insulator layers etc.) forms features for the memory devices (claimed memorization layer). DeVilliers ‘016, in [0037], discloses the formation of mandrels (claimed first structures) over the target layer and are patterns positioned in the same manner (lines that are parallel and spaced apart from each other), and forming sacrificial structures on the side surfaces of the mandrel that also becomes the sidewalls of the subsequently deposited masking layer formed, removing the spacers (i.e., anti-spacers) to thereby forming anti-spacers between the mandrels and masking patterns and DeVilliers ‘016, in [0039]-[0041], and Table 1, discloses forming (transferring) the pattern (first etch pattern) in the target layer (via etching). DeVilliers, in [0074], discloses the formation of a second resist layer in other portions (not on portions that has the mandrels and the second masking layer pattern) that are subjected to lithography to form resist patterns (of the second resist layer) that are then subjected to the process of forming anti-spacers (i.e., forming a topcoat material on the resist patterns formed in other areas/portions, followed by spacer formation and subsequent filling of another masking layer and removing the spacer to form another set of anti-spacers) and is the claimed second anti-spacers, and transferring the patterns to the underlying layer (target layer, to form structures in the IC device layer of the substrate , claimed second etch pattern) (claim 1). DeVilliers ‘016, in [0097]-[0104], discloses the forming of mandrels (claimed first structures) on the substrate (substrate includes hard mask layers, semiconductor layers, memory device forming layers, see [0027]-[0031]), coating a solution (claimed first overcoat, acid or base solution) that is coated over the mandrels and the exposed portions of the underlying hard mask layer (target layer), subjected the resulting structure with solution overcoat to a bake process (claimed annealing) resulting in the formation of anti-spacers (on the top sides and sidewalls of the mandrels, spacer, spacer material is formed to be eventually removed called anti-spacers), followed by removing the solution on the exposed portions of the hard mask (target layer) (forming trenches), coating a second masking layer over the now exposed surfaces of the hard mask layer (target layer, exposed due to removing of the acid/base solution that was coated earlier resulting in the claimed trench formation) wherein the second masking layer is blanked deposited over the spacers and the exposed surfaces of the underlying hard mask layer (claimed filling the plurality of trenches with filler material) (claim 4). DeVilliers ‘016, in [0043], [0051], and [0063], discloses that the solution (top coat) coated onto the mandrels include components that diffuse into the peripheral surfaces of the mandrel (top and side surfaces of the mandrel) causing a change in the surface of mandrels i.e., altering top surface portions and sidewall surface portions of the mandrels thereby forming anti-spacers on the periphery of the mandrels (claim 5). DeVilliers ‘016, in [0102], [0106], and [0112], discloses that second masking layer is blanket deposited to cover the mandrels, the anti-spacers such that the second masking layer overlies the top portions of the mandrels and anti-spacers and an etch process (claimed controlled recess etch step) is performed to remove the topcoats of the second masking layer (filler material) so as to expose the top surface of the anti-spacers (claim 6). DeVilliers ‘016, in [0036], [0050], and [0051], discloses the formation of mandrels (first structures) and filling the space between the mandrels with a second masking layer (covering the mandrels) and baking the resulting second masking layer coated mandrels so as to form chemically altered portions called “anti-spacers” on the sidewalls of the mandrels wherein the altered portions that form the anti-spacers includes both the sidewall surface material of the mandrels and the adjacent portions of the second masking material (claimed filler material) wherein the chemically altered portions i.e., the anti-spacers are formed due to the acid diffused from the sidewalls of the mandrels to (out-diffusion of acid from the mandrels) the adjacent portions of the second masking material (claim 7). DeVilliers ‘016, in [0035], [0038], [0052], [0106], [0112], discloses that the outer surface of the anti-spacers (sacrificial structures) is exposed by etching the overlying second masking material (controlled recess etch) (claim 9). DeVilliers ‘016, in [0050]-[0051], and [0075], discloses that the anti-spacers (first anti-spacer material) formed that are self-aligned to the mandrels (formed on the sidewall surfaces of the mandrels) are removed via a developer (solvent) (claim 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 11-14, is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2010/0130016 (hereinafter referred to as DeVilliers ‘016) in view of U. S. Patent Application Publication No. 2016/0181100 (hereinafter referred to as deVilliers ‘100).
DeVilliers ‘016, in the abstract, and in [0027]-[0033], discloses a process of forming patterns (claimed parallel final trenches having a final first pitch) in the substrate the substrate includes target layer wherein the target layer (multiple layers of metal layer, semiconductor layer, insulator layers etc., includes hard mask layers) forms features for the memory devices (claimed memorization layer). DeVilliers ‘016, in [0008], [0037], discloses the formation of mandrels (claimed first structures) over the target layer and are patterns positioned in the same manner (lines that are parallel and spaced apart from each other), wherein the mandrels (the mandrels original width form two features and two spaces) form by pitch multiplication via anti-spacer formation a final pitch (claimed first pitch) that is 1/4th the pitch of the mandrel i.e., the mandrel is quadruple the first pitch and forming sacrificial structures (anti-spacer material) on the side surfaces of the mandrel that also becomes the sidewalls of the subsequently deposited masking layer formed, removing the spacers (i.e., anti-spacer) to thereby forming anti-spacers between the mandrels and masking patterns (filler lines). DeVilliers ‘016, in [0124]-[0129], discloses the mandrels that have a first pitch, forming spacers on the side surfaces of the mandrels and coating the filler material (the second masking layer) in the space between the mandrels with the spacers such that the pattern constitutes the first pattern of mandrels and the spacers that becomes the anti-spacer material and the intervening masking material i.e., the mandrel and intervening second masking material (filler) is three times the width of the anti-spacer material width (the claimed first width) and removing the anti-spacer to form the pattern that is transferred to the underlying target layer (hard mask layer) that has a pitch that is half the mandrel pitch but twice the final pitch (claimed first pitch). DeVilliers ‘016, in [0039]-[0041], and Table 1, discloses forming (transferring) the pattern (first etch pattern) in the target layer (via etching). DeVilliers, in [0074], and [0130]-[0133], and [0136], discloses the formation of a second resist layer in other portions (not on portions that has the mandrels and the second masking layer pattern i.e., shifted from the first mandrels) that are subjected to lithography to form resist patterns (of the second resist layer) and/or forming another set of mandrels with a third masking layer in addition to the first mandrels and intervening features (filler material) wherein the third masking layer is processed to form a second set of anti-spacers (i.e., forming a topcoat material on the resist patterns formed in other areas/portions, followed by spacer formation and subsequent filling of third masking layer and removing the spacer to form the second set of anti-spacers and is the claimed second stencil trenches) that has a pitch that is half the pitch of the mandrel (such that the third masking layer pattern is at a distance of the second anti-spacer material width from the first mandrel) and transferring the patterns (claimed second etch pattern, second anti-spacer trench or second stencil trench) to the underlying layer (target layer, to form structures in the IC device layer of the substrate , claimed second etch pattern on to the underlying target layer that includes first and second hard mask layers) such that all the patterns (first and second stencil trenches or first and second anti-spacer trench) transferred to the underlying layer (target layer) has the same final width (claimed first width) i.e., DeVilliers ‘016, in [0132], and [0133], discloses that the pitch can be multiplied by performing additional processes using anti-spacers so as to multiply the pitches and for each anti-spacer formation and transfer via etch, the pitch is reduced by half of the pitch of the previous pitch and further anti-spacer and lithography, and etch results in further reducing the pitch of the final pitch by half the amount of the immediate preceding pitch (claims 11-14).
The difference between the claims and DeVilliers ‘016 is that DeVilliers ‘016 does not disclose the formation of a first block mask or a second block mask positioned over the first or second trenches (first or second hard mask layer, underlying layers) as also recited in claims 2-3.
deVilliers ‘100, in [0028], discloses the formation of a combined pattern wherein the anti-spacer material is removed (spacers) leaving behind the mandrels and filler material patterns with the narrow trench formation (by removal of spacers), and deVilliers ‘100, in [0030]-[0031], discloses the formation of a upper pattern (block pattern) on the mandrels and filler patterns (combined pattern) wherein the upper pattern is formed by forming a resist layer atop the combined patterns and lithography patterning the resist layer to form a mask (block mask) that reveals a portions of the combined pattern (portions of the underlying mandrels and portions of the filler material patterns) and deVilliers ‘100, in [0034] discloses transferring the block patterns to the underlying target layer wherein the block pattern (elevationally combined pattern, [0035]) include multiple patterns (first and second block pattern) that are transferred to the underlying target layer.
Therefore, it would be obvious to a skilled artisan to modify DeVilliers ‘016 by using elevationally combined pattern (block patterns) as taught by deVilliers ‘100 because DeVilliers ‘016 does not prohibit further processing of the mandrels and intervening masking features formed on the target layer and deVilliers ‘100 discloses that using a block pattern enables the selective covering of some of the uncovered spacers (anti-spacer) and also the formation of a elevationally combined pattern mask that can transfer multiple pattern structures such as slots, contacts and other mask structures to the underlying target layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daborah Chacko-Davis whose telephone number is (571) 272-1380. The examiner can normally be reached on 9:30AM-6:00PM EST Mon-Fri. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark F. Huff can be reached on (571) 272-1385. The fax phone number for the organization where this application or proceeding is assigned is 571-272-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DABORAH CHACKO-DAVIS/Primary Examiner, Art Unit 1737 May 2, 2026.
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