Prosecution Insights
Last updated: October 01, 2026
Application No. 17/989,554

ELECTRONIC PACKAGE

Final Rejection §103
Filed
Nov 17, 2022
Priority
May 29, 2020 — TW 109118096 +1 more
Examiner
FAN, SU JYA
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co., Ltd.
OA Round
6 (Final)
76%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
723 granted / 953 resolved
+7.9% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
42 currently pending
Career history
1008
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
19.6%
-20.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 953 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment The following office action is in response to the amendment and remarks filed on 5/18/26 Applicant’s amendment to claims 1 is acknowledged. Claims 5, 7, 8 and 11-22 are canceled. Claims 1-4, 6, 9 and 10 are pending and claims 3, 4 and 10 are withdrawn. Claims 1, 2, 6 and 9 are subject to examination at this time. Response to Arguments Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gu, CN 106033755 A (see attached English machine translation) in view of Choi et al., US Publication No. 2015/0179588 A1 (of record). Gu teaches: 1. An electronic package, comprising (see fig. 3): a carrier (310) having a function pad (320); an electronic component (340) disposed on the carrier; a shielding structure (320/330/332) including a single continuous bonding wire disposed on the same function pad (e.g. See page 9, “In an example, lead rail can be continuously formed by a single lead without severing the lead so as to further improve the productivity…”), wherein the single continuous bonding wire includes a plurality of stitch bonds on the same function pad (e.g. See stitch bonding at page 7, “…each wire loop 332 has arc-shaped, two end rings by wire bonding is attached to conductive traces 320 on the wire bonding is known to those skilled in the art, such as ball bonding, stitch bonding...”), each of a plurality of bonding wire portions (320/330/332) is defined between two adjacent stitch bonds of the single continuous bonding wire, wherein each of the plurality of bonding wire portions (320/330/332) includes (e.g. See fig. 3C annotated below for first line segment, second line segment, one end and other end) a first line segment and a second line segment, one end of the first line segment of one of the bonding wire portions is in contact with one end of the second line segment of another one of the bonding wire portions and the function pad (320), and other end of the first line segment of the one of the bonding wire portions and other end of the second line segment of the another one of the bonding wire portions are separated from each other and are away from the function pad (320); a package layer (350) encapsulating the electronic component and the shielding structure; and a shielding layer (360) formed on the package layer… See Gu at English machine translation pages 1-16, figs. 1-12. Regarding claim 1: Gu does not expressly teach the shielding layer directly electrically connected to the carrier. In an analogous art, Choi teaches: a shielding layer (170) formed on the packaging layer (160) and directly electrically connected to the carrier (110). See Choi at para. [0035] – [0047]. PNG media_image1.png 569 616 media_image1.png Greyscale 9. The electronic package of claim 1, wherein the shielding layer (360) is in contact (e.g. through intervening layers) with the shielding structure (320/330/332), fig. 3A. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gu with the teachings of Choi because ground lines in the carrier may function as paths for proving a ground path to the chips and shielding structure. See Choi at para. [0043]. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Choi, as applied to claim 1 above, in further view of Welch et al., US Publication No. 2011/0084378 A1. Regarding claim 2: Gu and Choi teach all the limitations of claim 1 above, but do not expressly teach: wherein a length of the first line segment and a length of the second line segment are not equal. In an analogous art, Welch teaches: (see fig. 5) wherein a length of the first line segment (e.g. segment right of center) and a length of the second line segment (e.g. segment left of center) are not equal, para. [0039] – [0040]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gu with the teachings of Welch because “The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer.” See Welch at Abstract. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Choi, as applied to claim 1 above, in further view of Morris et al. US Publication No. 2019/371738 A1 (of record). Regarding claim 6: Gu and Choi teach all the limitations of claim 1 above, but do not expressly teach: wherein the shielding structure is partially exposed from the packaging layer. In an analogous art, Morris teaches: (see figs. 2C-2E) wherein the shielding structure (20) is partially exposed from the packaging layer (32), para. [0032] – [0035]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gu with the teachings of Morris because exposing the ends of the wires (-i.e. shielding structure) increases the surface area for bonding the shielding layer. See Morris at para. [0033]. Relevant Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Convert, US 9508658 B1 (e.g. In fig. 1, Convert teaches a shielding wall 110.) Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 17 July 2026
Read full office action

Prosecution Timeline

Show 8 earlier events
Mar 28, 2025
Non-Final Rejection mailed — §103
Jun 13, 2025
Response Filed
Sep 11, 2025
Final Rejection mailed — §103
Dec 11, 2025
Request for Continued Examination
Dec 29, 2025
Response after Non-Final Action
Feb 18, 2026
Non-Final Rejection mailed — §103
May 18, 2026
Response Filed
Jul 21, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12727310
DISPLAY DEVICE
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Patent 12721137
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
2y 10m to grant Granted Aug 25, 2026
Patent 12713990
SEMICONDUCTOR PACKAGE
4y 4m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
76%
Grant Probability
87%
With Interview (+11.1%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 953 resolved cases by this examiner. Grant probability derived from career allowance rate.

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