DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5 and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (PG Pub. No. US 2015/0008428 A1) in view of Sunamura et al. (US 2014/0061810 A1), Yamazaki (PG Pub. No. US 2015/0034949 A1) and Yamamoto et al. (Pg Pub. No. US 2015/0069387 A1, hereinafter referenced as ‘Yamamoto-387’).
Regarding claim 1, Yamamoto teaches a semiconductor device (fig. 14D among others) comprising:
a first transistor (¶ 0246: 2200) comprising:
a first channel formation region (¶ 0175 & fig. 14D: channel formation region of 220 in substrate 400);
a first gate electrode (¶ 0253 & fig. 14D: 2200 includes gate electrode);
a first gate insulating layer between the first channel formation region and the first gate electrode (fig. 14D: unlabeled layer between channel region of 400 and gate electrode of 2200; since 2200 is a transistor, it implicitly includes a gate insulating layer);
a first source region (implicit, 2200 is a transistor which includes a source region, such as shaded region of fig. 14D); and
a first drain region (fig. 14D: implicit, 2200 is a transistor which includes a drain region, such as second shaded region of fig. 14D),
a second transistor (¶ 0117: 450) comprising:
a second gate electrode (¶ 0117: 401);
a second gate insulating layer (¶ 0117: 402) over the second gate electrode (fig. 12B, 14D: 402 disposed over 401);
an oxide semiconductor layer (¶ 0117: 404) comprising a second channel formation region over the second gate insulating layer (figs. 12B, 14D: 404 comprises a channel formation region and disposed over 402);
a third gate insulating layer (¶ 0117: 408) over the second channel formation region (figs. 12B, 14D: 408 disposed over 404);
a third gate electrode (¶ 0117: 410) over the third gate insulating layer (figs. 12B, 14D: 410 disposed over 408);
a source electrode (¶ 0117: 406a); and
a drain electrode (¶¶ 0117, 0251 & figs. 12B, 14D: 406b and/or 2205), and
an insulating layer (¶ 0251: 2204) over the second transistor (fig. 14D: 2204 disposed over 450),
wherein a bottom of the third gate electrode comprising a region below a bottom of the second channel formation region (figs. 12C, 14D: portion of 410 extends below a bottom of channel portion of 404),
wherein one of the first source region and the first drain region is electrically connected to one of the source electrode and the drain electrode (fig. 14D: source/drain region of 2200 electrically connected to at least one of 406a and 406b), and
wherein the first channel formation region comprises silicon (¶ 0175: 400, including a channel formation region of 2200, comprises silicon).
Yamamoto does not explicitly teach the semiconductor device further comprising:
the source electrode and the drain electrode are disposed over the insulating layer,
a conductive layer is provided in the same layer as the source electrode and the drain electrode and comprises the same material as the source electrode and the drain electrode,
wherein the conductive layer is electrically connected to the second gate electrode and the third gate electrode, and
wherein the first gate electrode does not overlap with the second gate electrode and the third gate electrode.
Sunamura teaches a semiconductor device (¶ 0092 & fig. 1B: 200) including source/drain electrodes (285) and a conductive layer (289), wherein the conductive layer is provided in the same layer and comprises a same material as source/drain electrodes (¶ 0092: 285 and 289 formed from conductive material of wiring layer 170) and disposed over an insulating layer (fig. 1B: at least upper portions of 285/289 disposed over lower portions of insulating layer 172), wherein the conductive layer is electrically connected to a gate electrode (¶ 0101 & fig. 1A: 289 electrically coupled to 222, similar to third gate 410 of Yamamoto).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Yamamoto with a conductive layer in a same layer as second source and drain electrodes (above insulating layer 2204 of Yamamoto, and/or insulating layer insulating layer 172 of Sunamura), as a means to provide interconnect portions 285/289 on the surface of the interlayer insulating film, allowing for electrical connection to external circuitry, including power, ground and signals.
Yamamoto in view of Sunamura does not teach:
wherein the conductive layer is electrically connected to the second gate electrode, and
wherein the first gate electrode does not overlap with the second gate electrode and the third gate electrode.
Yamazaki teaches a semiconductor device (fig. 3C) including a second gate electrode (conductive film 401) electrically connected to a third gate electrode (¶ 0140: in at least one embodiment, 401 electrically connected to gate 410).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the conductive layer of Yamamoto in view of Sunamura to be electrically connected to both the second and third gate electrodes, as a means to increase on-state current and/or control threshold voltage of the corresponding transistor (Yamazaki, ¶ 0140).
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson’s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02.
Yamamoto in view of Sunamura and Yamazaki does not teach wherein the first gate electrode does not overlap with the second gate electrode and the third gate electrode.
Yamamoto-387 teaches a semiconductor device (fig. 16) including a first gate electrode (¶ 0225: 235b of transistor 250, similar to gate electrode of 2200 of Yamamoto) and a second gate electrode (¶ 0229: 255b, similar to 401 of Yamamoto), wherein the first gate electrode does not overlap with the second gate electrode (fig. 16: 235b does not vertically overlap 255b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the transistors of Yamamoto in view of Sunamura and Yamazaki such that the gate electrodes do not overlap, as a means to provide a lower transistor (240 or 250 of Yamamoto-387, 2200 of Yamamoto) with sizes and/or densities suitable for high operating speed and/or threshold (Yamamoto-387, ¶ 0228). Furthermore, said artisan would recognize that such a configuration would include the first gate electrode of Yamamoto not overlapping with the second gate electrode and the third gate electrode.
Regarding claim 2, Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 teaches the semiconductor device according to claim 1,
wherein a length of the second channel formation region is less than or equal to 20nm (Yamamoto, ¶ 0124),
wherein a width of the second channel formation region is less than or equal to 20 nm (Yamamoto, ¶ 0124), and
wherein a thickness of the second channel formation region is greater than or equal to 10 nm (Yamamoto, ¶ 0135).
Regarding claim 5, Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 teaches the semiconductor device according to claim 1, wherein, in a plan view, the second gate electrode and one of the source electrode and the drain electrode do not overlap with each other (Yamamoto, fig. 14D: 401 and 2205 do not overlap in channel length or channel width directions).
Regarding claim 22, Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 teaches the semiconductor device according to claim 1, wherein the source electrode, the drain electrode, and the conductive layer comprise titanium (Sunamura, ¶ 0116: 285 and 289 include Ti-containing barrier films).
Regarding claim 23, Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 teaches the semiconductor device according to claim 1, comprising second and third gate electrodes (Yamamoto, 401 and 410).
Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 does not teach wherein the second gate electrode and the third gate electrode comprise molybdenum.
However, Sunamura teaches a device (fig. 10) including top and back gate electrodes (¶¶ 0092, 0154: 222, 210), and further teaches gate electrodes comprising molybdenum (¶ 0114: 222 comprises Mo).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second gate electrode and the third gate electrode of Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 with molybdenum, as a means to determine the effective work function of the semiconductor element (Sunamura, ¶ 0114).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, molybdenum is a suitable material to form gate electrodes, as evidenced by Sunamura.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 as applied to claim 1 above, and further in view of Yamazaki et al. (PG Pub. No. US 2013/0187150 A1, hereinafter referenced as ‘Yamazaki-150’).
Regarding claims 3-4, Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 teaches the semiconductor device according to claim 1, wherein the oxide semiconductor layer further comprises a second source region (Yamamoto, figs. 12B, 14C: portion of 404 overlapping 406a) and a second drain region (Yamamoto, figs. 12B, 14C: portion of 404 overlapping 406a), and a second channel formation region (Yamamoto, portion of 404 beneath 410 and between 406a and 406b).
Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 as applied to claim 1 above does not teach wherein each of the first source region and the first drain region has lower resistance than the first channel formation region, wherein each of the second source region and the second drain region has lower resistance than the second channel formation region, wherein a first impurity concentration is higher in each of the first source region and the first drain region than in the first channel formation region, or wherein an impurity concentration is higher in each of the second source region and the second drain region than in the second channel formation region.
Yamazaki-150 teaches a transistor (¶ 0094 & figs. 1A-1C, similar to 450 of Yamamoto), the transistor comprising an oxide semiconductor layer (¶ 0095: 106, similar to 404 of Yamamoto) including a source and drain regions (¶ 0111: source/drain regions 106b) and a channel formation region (¶ 0111: channel region 106b), wherein the source and drain regions have a lower resistance than the channel formation region (¶ 0112: 106b regions have lower resistance than 106a region), and
wherein an impurity concentration is higher in the source and drain region than in the second region (¶¶ 0208-209: regions 106b formed by adding impurities to 107 while 106a masked by gate 104).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first and second source regions and first and second drain regions of Yamamoto in view of Sunamura, Yamazaki and Yamamoto-387 with low resistance and high impurity concentration of Yamazaki-150, as a means to provide a highly integrated transistor with enhanced performance (Yamazaki-150, ¶¶ 0012-0016).
Allowable Subject Matter
Claims 8-12 and 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to teach or clearly suggest the limitations stating:
“a third transistor comprising:
a fourth gate electrode;
the second gate insulating layer over the fourth gate electrode;
the oxide semiconductor layer comprising a third channel formation region over the second gate insulating layer;
the third gate insulating layer over the third channel formation region;
a fifth gate electrode over the third gate insulating layer;
the first electrode; and
a third electrode” as recited in claim 8, and
“a fourth insulator over the second transistor,
wherein the fourth conductor and the fifth conductor are provided over the fourth insulator,
wherein, in a plane perpendicular to a channel length direction, the second channel formation region is surrounded along all sides by the second conductor and the third conductor,
wherein the fourth conductor is electrically connected to the third region,
wherein the fifth conductor is electrically connected to the fourth region, wherein the sixth conductor is electrically connected to the second conductor and the third conductor, and
wherein the fourth conductor, the fifth conductor, and the sixth conductor are provided in the same layer” as recited in claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 and 22-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818