DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 01/23/2026. Claims 1-15 and 17-19 are pending in this application. Claims 1, 8-9, 14-15, and, 17-19 are amended. Claims 16 and 20 are deleted.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 02/12/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, 15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Suzuki et al. (US 2009/0242995; hereinafter ‘Suzuki’).
Regarding claim 1, Wang teaches a transistor structure (100, FIGS. 21A and 21B, [0078]) comprising:
a substrate (50, [0011]) with a fin structure (64A and 64B; hereinafter ‘64’);
an isolation wall (83, [0028]) clamping sidewalls of the fin structure (83 surrounding sidewalls of 64);
a shallow trench isolation region (a trench region defined at an interface between the isolation wall structure 85 and the supporting beam 87, [0041]; hereinafter ‘STI’) surrounding the isolation wall (STI surrounding 83);
at least one supporting beam (87) sustaining an upper portion of the isolation wall (87 sustaining an upper portion of 83) and is separate from and above a bottom portion of the isolation wall (87 is separate from and above a bottom portion of 83), wherein the at least one supporting beam is disposed within the shallow trench isolation region (87 is disposed within STI); and
a gate region (72 and 97, FIGS. 14A and 17, [0078, 0080]; hereinafter ‘GR’) above the fin structure and the isolation wall (GR above 64 and 83);
wherein the isolation wall is configured to prevent the fin structure from collapsing (83 provides structural support for 64 to prevent collapse, [0084]).
Wang does not teach the transistor structure wherein the at least one supporting beam extends laterally form the upper portion of the isolation wall.
Suzuki teaches a transistor structure (Fig. 10(c), [0028]) wherein the at least one supporting beam (50x including 17A and 18A, [0.128-0129]) extends laterally form the upper portion of the isolation wall (50x extending laterally along the upper boundary portions of the isolation wall including 21, 22, and 23, [0130-0131]).
As taught by Suzuki, one of ordinary skill in the art would utilize and modify the above teaching into Wang to obtain and achieve the transistor structure wherein the at least one supporting beam extends laterally form the upper portion of the isolation wall as claimed, because laterally extending insulating structures adjacent isolation regions reinforce and stabilize isolation-adjacent semiconductor regions while maintaining structural integrity of narrow semiconductor features [0129].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Suzuki in combination with Wang due to above reason.
Regarding claim 5, Wang in view of Suzuki teaches the transistor structure in claim 1, wherein the gate region (Wang: GR, FIGS. 21A and 21B) comprising a gate dielectric layer (96, [0067]) over the fin structure substrate(96 over 64), a gate conductive layer (98) over the gate dielectric layer (98 over 96), and a cap layer (95, [0073]) over the gate conductive layer (95 over 98).
Regarding claim 6, Wang in view of Suzuki teaches the transistor structure in claim 5, wherein the isolation wall is configured to prevent the fin structure from collapsing during the formation of the gate dielectric layer, the gate conductive layer, and the cap layer (Wang: 83 prevents 64 from collapsing in subsequent processing, [0084]).
Regarding claim 7, Wang in view of Suzuki teaches the transistor structure in claim 1, further comprising a spacer layer (Wang: 73, FIG. 13, [0080]) on a sidewall of the gate region (73 on a sidewall of GR).
Regarding claim 15, Wang teaches a transistor structure (100, FIG. 21B, [0079]) comprising:
a substrate (50, [0011]) with a fin structure (64A and 64B; hereinafter ‘64’);
a shallow trench isolation region (a trench region defined at an interface between the isolation wall structure 85 and the supporting beam 87, [0041]; hereinafter ‘STI’);
a composite structure (83 and 85, [0048]; hereinafter ‘CS’) surrounded by the shallow trench isolation region (85 surrounded by STI) and comprising a supporting wall (83) clamping sidewalls of the fin structure (83 clamping sidewalls of 64) and at least one supporting beam (87) sustaining an upper portion of the supportive wall (87 sustaining an upper portion of 83), wherein the at least one supporting beam is separate from and above a bottom portion of the supporting wall (87 is separate from and above a bottom portion of 83), and the at least one supporting beam is disposed within the shallow trench isolation region (87 is disposed within STI); and
a gate region (72 and 97, FIGS. 14A and 17, [0078, 0080]; hereinafter ‘GR’) above the fin structure and the composite structure (GR above 64 and CS);
wherein the composite structure is configured to prevent the fin structure from collapse (CS prevents 64 from collapse, [0084]).
Wang does not teach the transistor structure wherein the at least one supporting beam extends laterally form the upper portion of the supporting wall.
Suzuki teaches a transistor structure (Fig. 10(c), [0028]) wherein the at least one supporting beam (50x including 17A and 18A, [0.128-0129]) extends laterally form the upper portion of the isolation wall (50x extending laterally along the upper boundary portions of the isolation wall including 21, 22, and 23, [0130-0131]).
As taught by Suzuki, one of ordinary skill in the art would utilize and modify the above teaching into Wang to obtain and achieve the transistor structure wherein the at least one supporting beam extends laterally form the upper portion of the supporting wall as claimed, because laterally extending insulating structures adjacent isolation regions reinforce and stabilize isolation-adjacent semiconductor regions while maintaining structural integrity of narrow semiconductor features [0129].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Suzuki in combination with Wang due to above reason.
Regarding claim 17, Wang in view of Suzuki teaches the transistor structure in claim 15, wherein the upper portion of the supporting wall extends upward from the bottom portion of the supporting wall (Wang: the upper portion of 83 extend in a vertical direction, FIG. 21B).
Regarding claim 18, Wang in view of Suzuki teaches the transistor structure in claim 15, wherein the supporting wall and the at least one supporting beam are made of nitride (Wang: 83 and 87 are made of nitride, [0028, 0043]).
Regarding claim 19, Wang in view of Suzuki teaches the transistor structure in claim 16, Wang does not teach the transistor structure wherein the at least one supporting beam abuts against the supporting wall.
Suzuki teaches the transistor structure wherein the at least one supporting beam abuts against the supporting wall (50x abuts against SW, Fig. 10(c)).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Suzuki to obtain and achieve the transistor structure the at least one supporting beam abuts against the supporting wall as claimed, because laterally extending structure support vertically extending isolation sidewall structures while maintaining substrate regions between trench portions and isolation regions, thereby improving structural stability of narrow semiconductor features [0129].
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Suzuki (US 2009/0242995), and further in view of Utomo et al. (US 2014/0191297; hereinafter ‘Utomo’).
Regarding claim 2, Wang in view of Suzuki teaches the transistor structure in claim 1, but does not teach the transistor structure wherein the isolation wall clamps four sidewalls of the fin structure.
Utomo teaches a transistor structure (FIGS. 10A-10C, [0033-0035]) wherein the isolation wall (20, [0093]) clamps four sidewalls of the fin structure(20 contacts and surrounds all sidewalls of 12, which is the fin structure, [0064, 0093]).
As taught by Utomo, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Suzuki to obtain and achieve the transistor structure wherein the isolation wall clamps four sidewalls of the fin structure as claimed, because this configuration not only ensures perfect electrical isolation from the substrate, but also enhances mechanical stability and provides uniform stress distribution across the fin structure [0090, 0093].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Utomo in combination with Wang in view of Suzuki due to above reason.
Regarding claim 3, Wang in view of Suzuki and Utomo teaches the transistor structure in claim 2, further comprising a STI layer (Wang: 62, FIG. 21B, [0036]) surrounding the isolation wall (62 surrounding 83).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Suzuki (US 2009/0242995), further in view of Wu et al. (US 2013/0056795; hereinafter ‘Wu’).
Regarding claim 4, Wang in view of Suzuki teaches the transistor structure in claim 1, but does not teach the transistor structure further comprising a sheet channel layer disposed between the sidewalls of the fin structure and the isolation wall, wherein the sheet channel layer is formed by selective epitaxy growth.
Wu teaches a transistor structure (FIGS. 6A-6C, [0009]), further comprising a sheet channel layer (151, which is a thin layer, [0014, 0021]) disposed between the sidewalls of the fin structure and the isolation wall (151 disposed between 150 and 170), wherein the sheet channel layer is formed by selective epitaxy growth (151 is epitaxially grown by selective epitaxial growth, [0022]).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Suzuki to obtain and achieve the transistor structure further comprising a sheet channel layer disposed between the sidewalls of the fin structure and the isolation wall, wherein the sheet channel layer is formed by selective epitaxy growth as claimed, because the sheet channel layer, having a think thickness and a lower bandgap than that of the fin structure, improves electrostatic control and mitigates short-channel effects [0021, 0044]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Wang in view of Suzuki due to above reason.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Suzuki (US 2009/0242995), further in view of Hu et al. (US 2016/0163862; hereinafter ‘Hu’).
Regarding claim 8, Wang in view of Suzuki teaches the transistor structure in claim 7, but does not teach the transistor structure wherein a first conductive region is formed in a first concave under an original surface of the substrate.
Hu teaches a transistor structure (100, fig. 7, [0033]), wherein a first conductive region (132) is formed in a first concave under an original surface of the substrate (132 formed in a recess of 106).
As taught by Hu, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Suzuki to obtain and achieve the transistor structure wherein a first conductive region is formed in a first concave under an original surface of the substrate as claimed, because it achieves uniform epitaxial growth and stable junction formation [0033].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hu in combination with Wang in view of Suzuki due to above reason.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Suzuki (US 2009/0242995), further in view of Guillorn et al. (US 2018/0006159; hereinafter ‘Guillorn’).
Regarding claim 9, Wang in view of Suzuki teaches the transistor structure in claim 1, further comprising:
a first conductive region (Wang: 80, FIG. 21A, [0078]) between the gate region and the shallow trench isolation regions (80 between GR and STI, FIGS. 21A and 21B).
Wang in view of Suzuki does not teach the transistor structure further comprising a metal region between the gate region and the shallow trench isolation region; wherein at least two sides of the first conductive region contact to the metal region.
Guillorn teaches a transistor structure (100, FIGS. 15A and 15B, [0119]), further comprising a metal region (242, [0122]) between the gate region and the shallow trench isolation region (242 between 230 and 214, FIGS. 5B and 11A, [0088, 0110]); wherein at least two sides of the first conductive region (222, FIGS. 8A and 8B, [0101]) contact to the metal region (at least two sides of 222 contact to 242).
As taught by Guillorn, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Suzuki to obtain and achieve the transistor structure further comprising a metal region between the gate region and the shallow trench isolation region; wherein at least two sides of the first conductive region contact to the metal region as claimed, because forming the metal region conformally on the first conductive region enlarges the S/D-metal interface, producing a low-resistance ohmic contact and improving current uniformity along the fin sidewalls [0067-0068].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Guillorn in combination with Wang in view of Suzuki due to above reason.
Regarding claim 10, Wang in view of Suzuki and Guillorn teaches the transistor structure in claim 9, wherein the shallow trench isolation region extends upward and above an original surface of the substrate (Wang: STI extends upward and above the original surface of 50, FIG. 21B).
Wang in view of Suzuki does not teach the transistor structure wherein the first conductive region is not over the shallow trench isolation region.
Guillorn teaches the transistor structure wherein the first conductive region (222, FIGS. 8A and 8B) is not over the shallow trench isolation region (222 is not over 214).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Guillorn g to obtain and achieve the transistor structure wherein the first conductive region is not over the shallow trench isolation region as claimed, because the conductive region is formed with sufficient separation from the surrounding structures to prevent merging, thereby ensuring electrical isolation and improving overall device stability [0102].
Regarding claim 11, Wang in view of Suzuki and Guillorn teaches the transistor structure in claim 9, Wang in view of Suzuki does not teach the transistor structure wherein the metal region contacts a top surface and a sidewall of the first conductive region.
Guillorn teaches the transistor structure wherein the metal region contacts a top surface and a sidewall of the first conductive region (242 contacts the top surface and the sidewall of 222, FIG. 15A).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Guillorn to obtain and achieve the transistor structure wherein the metal region contacts a top surface and a sidewall of the first conductive region as claimed, because utilizing sidewall contact increases interfacial contact area and thereby reduces contact resistance [0067-0068].
Regarding claim 12, Wang in view of Suzuki and Guillorn teaches the transistor structure in claim 9, further comprising an L shape isolator under a bottom of the first conductive region (Wang: 65 under the bottom of 80 has the L-shape, FIG. 21A, [0056]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Suzuki (US 2009/0242995), further in view of Schulz (US 2006/0189043).
Regarding claim 13, Wang in view of Suzuki teaches the transistor structure in claim 1, further comprising
a channel region (Wang: the exposed top region of 64 within 89, FIGS. 15 and 21A, [0066]; hereinafter ‘64T’); and
a first conductive region (80) electrically contacting to the channel region (80 electrically contacting to 64T through 65, FIG. 13, [0056]);
wherein a bottom of the gate region outside the fin structure (the bottom of 72 of GR positioned outside 64, FIG. 14A).
Wang in view of Suzuki does not teach the transistor structure further comprising wherein a bottom of the gate region outside the fin structure is lower than a bottom of the first conductive region.
Schulz teaches a transistor structure (FIGS. 14a and 14b, [0022]), further comprising wherein a bottom of the gate region (the bottom of 810 of the gate region including 810, 910, and 1222, [0044, 0050]) outside the fin structure (610, [0037]) is lower than a bottom of the first conductive region (the bottom of 810 is lower than a bottom of the 1310, [0052])
As taught by Schulz, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Suzuki to obtain and achieve the transistor structure further comprising wherein a bottom of the gate region outside the fin structure is lower than a bottom of the first conductive region as claimed, because the gate spacer is formed lower than the source/drain regions in order to achieve a planarized gate electrode, thereby reducing step height and improving chemical-mechanical polishing uniformity of the gate structure [0010-0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Schulz in combination with Wang in view of Suzuki due to above reason.
Regarding claim 14, Wang in view of Suzuki and Schulz teaches the transistor structure in claim 13, wherein the bottom of the gate region outside the fin structure is over a part of the shallow trench isolation region (Wang: the bottom of 72 corresponds to the bottom of 74 is over the part of 62, since 62 is STI layer, FIGS. 14A and 14C, [0036]).
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/3/26
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