DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 04/15/2026 amendments of claims 1,3 and 5 have been noted and entered.
The 04/15/2026 cancellation of claims 2 and 4 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 6-9, filed 04/15/2026, with respect to the rejection(s) of claim(s) 1-4, 6-7 and 9 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Lin et al, US 20230009347 A1 (Lin) and Savant et al, US 20210407861 A1 (Savant).
New Grounds of Rejection
New grounds of rejection, prior art reference Lin et al, US 20230009347 A1 (Lin) and Savant et al, US 20210407861 A1 (Savant) appear below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Disney, US 20030060001 A1 (Disney) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Lin et al, US 20230009347 A1 (Lin).
Regarding claim 1; Disney teaches a semiconductor structure comprising:
a substrate (Disney: Fig (5K): 100);
a gate dielectric layer (102a+106) on the substrate (100),
wherein the gate dielectric layer (102a+106) comprises two sidewall portions (106) and a horizontal portion (102a), and the horizontal portion (102a) is located between the two sidewall portions (106),
wherein the height of the horizontal portion (102a) is lower than the height of the two sidewall portions (106), and the horizontal portion (102a) and the two sidewall portions (106) are perpendicular to each other;
a gate conductive layer (113a) located on the horizontal portion (102a) of the gate dielectric layer,
wherein the gate conductive layer (113a) and the gate dielectric layer (102a+106) are combined into a gate,
a plurality of dummy gates are located beside the gate, wherein the gate comprises a long side and a short side, the long side having a length greater than the short side, and an extending direction of the long side is defined as a longitudinal direction, wherein a length of the gate is longer than a length of the dummy gate in the longitudinal direction;
a first spacer and a second spacer disposed on each sidewall portion; and
a contact etching stop layer covering the second spacer and the substrate,
wherein the contact etching stop layer directly contacts the gate dielectric layer and the second spacer.
PNG
media_image1.png
892
702
media_image1.png
Greyscale
Disney does not teach a plurality of dummy gates are located beside the gate, wherein the gate comprises a long side and a short side, the long side having a length greater than the short side, and an extending direction of the long side is defined as a longitudinal direction, wherein a length of the gate is longer than a length of the dummy gate in the longitudinal direction.
However, Chern teaches a plurality of dummy gates (Chern: Annotated Fig (4B) shared in this OA: 204D) are located beside the gate (204), wherein the gate (204) comprises a long side (the side along the Y – Longitudinal Direction) and a short side (the side along the X – Horizontal Direction), the long side (the side along the Y – Longitudinal Direction) having a length greater than the short side (the side along the X – Longitudinal Direction), and an extending direction of the long side (the side along the Y – Longitudinal Direction) is defined as a longitudinal direction (the Y – Longitudinal Direction), wherein a length of the gate (204) is longer than a length of the dummy gate (204D) in the longitudinal direction (the Y – Longitudinal Direction).
PNG
media_image2.png
659
912
media_image2.png
Greyscale
Disney and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Disney by introducing the dummy gates as disclosed in Chern to improve the outcomes of some of the etching processes on the gate structures leading to a more reliable device and a more efficient production process.
Disney in view of Chern does not teach a first spacer and a second spacer disposed on each sidewall portion; and a contact etching stop layer covering the second spacer and the substrate, wherein the contact etching stop layer directly contacts the gate dielectric layer and the second spacer
Lin teaches teach a first spacer (Lin: Fig (15): 1122) and a second spacer (1124) disposed on each sidewall portion (side walls of 1504); and a contact etching stop layer (630A, 630B) covering the second spacer (1124) and the substrate (302), wherein the contact etching stop layer (630A, 630B) directly contacts the gate dielectric layer (1502) and the second spacer (1124).
Disney in view of Chern and Lin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Disney in view of Chern by constructing the two spacer layers and the etch stop layer as disclosed in Lin to improve the insulation of the device against any short circuit possibilities thus leading to a more reliable device.
PNG
media_image3.png
691
928
media_image3.png
Greyscale
Regarding claim 6; Disney in view of Chern in further view of Lin teaches all the limitations of the semiconductor structure of claim 1.
Further, Disney teaches wherein a bottom surface of the horizontal portion (Disney: Fig (5K): 102a) is aligned with a bottom surface of the two sidewall portions (106).
Regarding claim 7; Disney in view of Chern in further view of Lin teaches all the limitations of the semiconductor structure of claim 1.
Further, Disney teaches wherein a bottom surface of the horizontal portion (Disney: Fig (5K): 102a) is aligned with a top surface of the substrate (100).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Disney, US 20030060001 A1 (Disney) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Lin et al, US 20230009347 A1 (Lin) in further view of Savant et al, US 20210407861 A1 (Savant)
Regarding claim 9; Disney in view of Chern in further view of Lin teaches all the limitations of claim 1.
While Disney in view of Chern teaches a difference in height between the horizontal portion of the gate dielectric layer (Disney: Fig (5J): 102a) and its sidewalls (116), it does not explicitly specify the ratio between the heights and thus it fails to teach wherein the ratio of a height of the horizontal portion to a height of the sidewall portion is between 0.7 and 0.95.
Savant teaches wherein the ratio of a height of the horizontal portion (Savant: Annotated Fig (5A) shared in this OA: Horizontal Portion) to a height of the sidewall portion (Sidewall Portion) is between 0.7 and 0.95 ([0048]: “The formation of opening 470 can be followed by etching work function stacks 301A and 301B to form trench 570... In some embodiments, gate dielectric layer 303 can be partially etched due to process variations during or after the wet etching process. In some embodiments, gate dielectric layer 303 can be partially removed by a thickness ranging from about 3 Å to about 7 Å. In some embodiments, a ratio of the thickness partially removed from gate dielectric layer 303 to the thickness of gate dielectric layer 303 can range from about 0.2 to about 0.5.", given that the dielectric layer loses about 0.2 to 0.5 of its thickness in the area under the trench 570, this means that the horizontal portion height ratio to the height of the sidewall portion not etched will be in the range of 0.8 to 0.5 which matches the ranges recited in the instant claim).
Disney in view of Chern in further view of Lin and Savant are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Disney in view of Chern in further view of Lin by removing a portion of the dielectric layer to establish more control over the current passing in the channel of the transistor via the gate potential leading to a more reliable device.
PNG
media_image4.png
737
1264
media_image4.png
Greyscale
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Disney, US 20030060001 A1 (Disney) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Lin et al, US 20230009347 A1 (Lin) in further view of Liu et al, US 20240128313 A1 (Liu).
Regarding claim 3; Disney in view of Chern in further view of Lin teaches all the limitations of the semiconductor structure of claim 1.
However, Disney in view of Chern in further does not teach wherein a bottom surface of the first spacer and a bottom surface of the second spacer are aligned with a top surface of the sidewall portion.
Lin teaches a second spacer (Lin: Fig (15): 1124).
Disney in view of Chern and Lin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Disney in view of Chern by constructing a second spacer as disclosed in Lin to improve the insulation of the gate structure against undesired current leakage.
Disney in view of Chern in further view of Lin does not teach wherein a bottom surface of the first spacer are aligned with a top surface of the sidewall portion.
Liu teaches wherein a bottom surface of the first spacer (Liu: Fig (1G): 1171, 1172) are aligned with a top surface of the sidewall portion (1081’, 1082’).
Disney in view of Chern in further view of Lin and Liu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Disney in view of Chern in further view of Lin by introducing the spacers disposed on the sidewalls as disclosed in Liu to improve the isolation of the gate structure against current leakage.
PNG
media_image5.png
649
960
media_image5.png
Greyscale
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights