DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding the 35 USC 112(a) and 112(b) rejections of claims 9 and 21, Applicant’s cancellation of these claims has rendered these rejections moot.
Regarding the rejection of the claims under 35 USC 103, Applicants arguments and amendments have been fully considered. However, further search and consideration have prompted the new grounds of rejection presented herein.
Applicant argues Crucially, in Matsunaga's FIG. 9, it is the first layer of wire (23), which has larger surface area, that is electrically connected to the gate (11) of transistor (9a). This teaching-using a larger metal area for gate contacts while using smaller pads for source/drain contacts-effectively teaches away from the claimed invention, which specifically requires a smaller first portion to be the interface directly above the gate.
However, Matsunaga has not disclosed that the above is crucial as alleged by Applicant.
Applicant further argues Since Matsunaga's own teaching actually leads away from the claimed invention-by utilizing a larger metal layer for gate contacts and smaller pads only for source/drain regions-there is no rational basis or suggestion in the prior art to motivate a person having ordinary skill in the art (PHOSITA) to reach the claimed configuration.
However, MPEP 2145 advises that A prior art reference that "teaches away" from the claimed invention is a significant factor to be considered in determining obviousness. However, "the nature of the teaching is highly relevant and must be weighed in substance. A known or obvious composition does not become patentable simply because it has been described as somewhat inferior to some other product for the same use." In re Gurley, 27 F.3d 551, 553, 31.
Matsunaga has not even described making the pad 31 larger/longer than that of the wire 23 would be inferior.
MPEP 2145 further advises that "a reference does not teach away if it merely expresses a general preference for an alternative invention but does not criticize, discredit or otherwise discourage investigation into the invention claimed."
Matsunaga has simply shown in FIG. 9 that the pad 31 is smaller/shorter than that of the wire 23, but has not criticized, discredited or otherwise discouraged the modification as proposed below. Accordingly, Matsunaga does not teach away from the invention as claimed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11, 13-15, 20, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20050051803A1 (“Matsunaga”) in view of US 20090134471 A1 (“Chatterjee”), further in view of US20060244741A1 (“Kimura”), further in view of Waller, Mark, “How to stop the antenna effect from destroying your circuit” available at www.edn.com/how-to-stop-the-antenna-effect-from-destroying-your-circuit/, September 20, 2021 (“Waller”).
RE: Claim 11, Matsunaga discloses A semiconductor device (55, [0082], FIG. 22), comprising:
at least one core device (61, [0082]) has a first metal gate (11 in second transistor group in FIG. 11 would be in 61, [0061]; 61 is configured from a second transistor group, [0083]; gate 11 is made of conductive film, [0043]; conductive film is made of copper, [0074]; Accordingly, the gate 11 is copper);
a first interconnect structure (23 for the second transistor group in FIG. 11, see [0022]) electrically connected to the first metal gate;
at least one input/output (I/O) device (63 in FIG. 22, [0082]), wherein the at least one I/O device has a second metal gate (11 in transistor 9a in FIG. 9 would be in first transistor group in 63, [0020]; In the memory 57, 59 and I/ O circuit 63, 65, these are made up of a first transistor group, [0083]);
a second interconnect structure (multi-layered wire for first transistor group in FIG. 9, [0060]) electrically connected to the second metal gate (11 in 9a in FIG. 9), wherein the second interconnect structure comprises a single layer (23, 31, [0060]) , and wherein the single layer is separated into a first portion (23) and a second portion (31); and
a jumper structure (37, 35, [0060]) overlying the single layer for bridging the first portion with the second portion, and
wherein the first portion is located directly above the second metal gate of the at least one I/O device and between the jumper structure and the second metal gate of the at least one I/O device (FIG. 9 shows 23 is located directly above 11 and between 37, 35 and 11 in 9a).
Matsunaga does not explicitly disclose:
a substrate having a logic circuit region thereon;
the at least one core device 61 is disposed on the substrate within the logic circuit region,
the at least one input/output (I/O) device 63 is disposed on the substrate within the logic circuit region;
the single layer is a single metal layer;
the single layer has a surface area greater than other layers of the second interconnect structure;
wherein the first portion has a surface area that is smaller than that of the second portion.
However, 55 is considered to include a substrate as 55 is a semiconductor chip, [0082]. A chip is defined as “a small wafer of semiconductor material that forms the base for an integrated circuit” (Merriam-Webster’s dictionary definition for “chip”, definitions 6a-6b, accessed at <https://www.merriam-webster.com/dictionary/chip> on April 24, 2025). Accordingly, 55 is considered to include a wafer of semiconductor material (which is considered a substrate) that forms the base for the circuits (i.e., 55, 61, 63, 65 in FIG. 22) thereon.
Matsunaga does not explicitly disclose that the semiconductor chip 55 is a logic circuit region.
However, 55 includes a logic circuit 61, [0082].
Accordingly, under a broadest reasonable interpretation, since the upper region of semiconductor chip 55 includes a logic circuit, the upper region of semiconductor chip 55 is considered a logic circuit region.
As a result, Matsunaga discloses:
a substrate (wafer of 55 in FIG. 22) having a logic circuit region (upper region of 55) thereon;
at least one core device (61) disposed on the substrate within the logic circuit region;
at least one input/output (I/O) device (63) disposed on the substrate within the logic circuit region.
Further, Matsunaga discloses the damascene is a process for forming a conductive film made of copper or the like on an interlayer dielectric film 27 with a concave portion formed therein and then polishing or rubbing this conductive film by chemical-mechanical polish (CMP) techniques to thereby form the wire 23, [0074].
Matsunaga further discloses the pad 31 was formed at the same time during formation of a first layer of wire 23, [0060].
Accordingly, it is understood that the wire 23 and the pad 31 are formed at the same time by the formation of the conductive film made of copper.
Alternatively, in the same field of endeavor, Chatterjee discloses a copper landing pad and copper interconnect line, [0008], and To limit the number of process steps and correspondingly limit manufacturing costs, the landing pad 122 could be made of the same material as the interconnect line 118, [0022], see FIG. 1A.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the pad out of copper as taught by Chatterjee as this would be the same material used for the wire 23 and would therefore limit the number of process steps and limit manufacturing costs as further taught by Chatterjee. As a result, the combination of 23, 31 would be made of copper.
Additionally, Matsunaga discloses By making the gate area and the wire width constant, the length of wire is an alternative to the antenna ratio. In short, this means that as the length of wire becomes larger, the antenna ratio also gets larger; the less the wire length, the less the antenna ratio, [0046]. Accordingly, the width of the wires 23 and 35 is the same and uniform.
In the same field of endeavor, Kimura discloses the wire 1002 and the wire 1003 have line widths approximately equal to those of the composite connection pad 113 a and the composite connection pad 113 b, respectively, [0152], see FIG. 10.
FIG. 10 shows each width of the pads 113a, 113b is uniform in top view, and respectively the same as each width of the wires 1002, 1003 in top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the width of the pad 31 in top view to be uniform and the same as the width of the wires 23, 35 as taught by Kimura in order to simplify manufacturing and/or to simplify the calculation of the antenna ratio, by making the ratio dependent on wire length, pad length rather than wire area and pad area.
In the same field of endeavor, Waller discloses in FIG. 3 on pg.4:
wherein a second interconnect structure comprises a single metal layer having a length greater than other layers of the second interconnect structure (Annotated FIG. 3 below shows an interconnect structure comprising a single metal layer having a length greater than other layers under the single metal layer of the second interconnect structure; Waller discloses the long track is metal, pg. 2, bottom paragraph), and
wherein the single metal layer is separated into a first portion and a second portion (Annotated FIG. 3 below shows the single metal layer is separated into a first portion and a second portion); and
a jumper structure overlying the single metal layer for bridging the first portion with the second portion (Annotated FIG. 3 shows a jumper structure overlying the single metal layer for bridging the first portion with the second portion),
wherein the first portion has a length that is smaller than that of the second portion (Annotated FIG. 3 shows the first portion has a length that is smaller than that of the second portion), and
wherein the first portion is located directly above the gate (Annotated FIG. 3 shows the first portion is located directly above the gate).
Waller further discloses A jumper breaks the long track close to the gate, reducing the charge that can accumulate during fabrication below a safe limit, pg. 4, first paragraph immediately below FIG. 3 and its caption.
It would have been obvious to one of ordinary skill in the art before the effective filing fate of the claimed invention to modify the single metal layer 23, 31 and the jumper structure 37, 35, 37 to have the configuration as taught by Waller in FIG. 3, and to introduce shorter wire layers under the single metal layer in FIG. 3 as also taught by Waller in FIG. 3 in order to reduce the charge that can accumulate during fabrication below a safe limit.
As the width of the wires is uniform and the same, and the width of the pad is the same as that of the wires, and the heights of the wires and pads are the same in FIG. 9:
the single layer (23, 31) would have a surface area greater than other layers of the second interconnect structure (23, 31 would have a surface area greater than the shorter wire layers under 23, 31);
wherein the first portion has a surface area that is smaller than that of the second portion (As modified, 23 is shorter than 31 and would therefore have a surface area smaller than that of 31).
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Annotated FIG. 3 of Waller
RE: Claim 13, Matsunaga in view of Chatterjee, Kimura, Waller discloses The semiconductor device according to claim 11, wherein the jumper structure comprises an upper metal layer (35 in FIG. 9 Matsunaga), a first via (lefthand 37) connecting the upper metal layer to the first portion, and a second via (righthand 37) connecting the upper metal layer to the second portion.
RE: Claim 14, Matsunaga in view of Chatterjee, Kimura, Waller discloses The semiconductor device according to claim 11, wherein the at least one core device has a first accumulative antenna ratio (Rmax2 in Matsunaga, [0083]), and the at least one I/O device has a second accumulative antenna ratio (Rmax1, [0083]), and wherein the first accumulative antenna ratio is greater than the second accumulative antenna ratio (In the memory 57, 59 and I/O circuit 63, 65, the maximum value Rmax1 of antenna ratio is 500 times. In contrast, in the logic circuit 61, the maximum value Rmax2 of antenna ratio is 3000 times, [0083]).
RE: Claim 15, Matsunaga in view of Chatterjee, Kimura, Waller discloses The semiconductor device according to claim 14, wherein the first accumulative antenna ratio is smaller than or equal to 5500 (Matsunaga discloses in the logic circuit 61, the maximum value Rmax2 of antenna ratio is 3000 times, [0083]).
RE: Claim 20, Matsunaga in view of Chatterjee, Kimura, Waller discloses The semiconductor device according to claim 11, wherein the at least one core device comprises a first gate oxide layer (21 in 61 in FIG. 22 Matsunaga, [0083]; the gate insulation film 19, 21 is a silicon oxide film (SiO2, SiON), [0040]) having a thickness that is equal to or less than 15 angstroms (the thickness of the gate insulation film 19, 21 is less than or equal to 6.0 nm, [0043]), and the at least one I/O device comprises a second gate oxide layer (19 in 63, [0083]; the gate insulation film 19, 21 is a silicon oxide film (SiO2, SiON), [0040]) having a thickness that is equal to or less than 50 angstroms (the thickness of the gate insulation film 19, 21 is less than or equal to 6.0 nm, [0043]).
RE: Claim 23, Matsunaga in view of Chatterjee, Kimura, Waller discloses The semiconductor device according to claim 11, wherein the second interconnect structure is configured such that an electrical path for the second metal gate sequentially comprises, in order of, the second metal gate, the first portion, the jumper structure, and the second portion, wherein the first portion is electrically coupled between the second metal gate and the jumper structure (As modified, the second interconnect structure is configured such that an electrical path for the second metal gate 11 sequentially comprises, in order of, the second metal gate 11, the first portion 23, the jumper structure 37, 35, and the second portion 31, wherein the first portion 23 is electrically coupled between the second metal gate 11 and the jumper structure 37, 35).
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsunaga in view of Chatterjee, Kimura, Waller as applied to claim 14 or 15, and further in view of US20050212558 (“Chung”).
RE: Claim 16, Matsunaga in view of Chatterjee, Kimura, Waller discloses The semiconductor device according to claim 15, wherein the second accumulative antenna ratio is smaller than or equal to 1000 (Matsunaga discloses In the memory 57, 59 and I/O circuit 63, 65, the maximum value Rmax1 of antenna ratio is 500 times, [0083]).
Matsunaga in view of Chatterjee, Kimura, Waller does not explicitly disclose wherein the at least one I/O device is 1.8V I/O device.
In the same field of endeavor, Chung discloses in a design where the core voltage VDDC is 1.0V and the I/O voltage is 1.8V, the transistors 104 and 106 will be clamped by the core voltage VDDC of 1.0V. The gate of the transistor 102 will be biased to 1.8V when the output needs to be a logic 0. Assuming the threshold voltage of the transistor 102 is 0.4V, when the output needs to be a logic 1, the gate of the transistor 102 is biased to a voltage lower than 1.4V, such as 1.3V. With a proper bias applied to the gate of the transistor 102, only a fraction of the I/O voltage 1.8V will reach the source of the transistor 104. By controlling the bias, the voltage difference across the transistor 102 can be controlled under a predetermined value, thereby preventing the same from damage, [0012].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bias the input/output (I/O) circuit 63 at 1.8V as taught by Chung in order to prevent damage when outputting logic as further taught by Chung.
RE: Claim 17, Matsunaga in view of Chatterjee, Kimura, Waller, Chung discloses The semiconductor device according to claim 16, wherein the 1.8V I/O device has a first single-layer antenna ratio of smaller than or equal to 500 (In the memory 57, 59 and I/O circuit 63, 65, the maximum value Rmax1 of antenna ratio is 500 times, [0083] in Matsunaga).
RE: Claim 18, Matsunaga in view of Chatterjee, Kimura, Waller discloses The semiconductor device according to claim 14, wherein the second accumulative antenna ratio is smaller than or equal to 2000 (In the memory 57, 59 and I/O circuit 63, 65, the maximum value Rmax1 of antenna ratio is 500 times, [0083] in Matsunaga).
Matsunaga in view of Chatterjee, Kimura, Waller does not explicitly disclose wherein the at least one I/O device is 2.5V I/O device.
However, in a similar field of endeavor, Chung discloses in a design where the core voltage VDDC is 1.0V, the I/O voltage is 2.5V, the voltage drop across the transistor 114 is 0.7V, and the threshold voltage of the same is 0.4V, the devices within the I/O driver 112 are biased by a set of differential biases. The gate of the transistor 114 can be biased to 2.5V when output needs to be logic 0, and 1.9V when output is to be a logic 1. When the output is to be a logic 0, with the bias of the transistor 114 and a voltage drop there across, only 1.8V will reach the source of the transistor 116, thereby preventing the transistor 114 from damage. The transistor 116 is biased to 1.4V whether the output is a logic 0 or 1. After another voltage drop, only 1.2V can reach the source of the transistor 118, thereby preventing the transistor 116 from damage, [0015].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bias the input/output (I/O) circuits 63, 65 at 2.5V as taught by Chung in order to prevent damage when outputting logic as further taught by Chung.
RE: Claim 19, Matsunaga in view of Chatterjee, Kimura, Waller, Chung discloses The semiconductor device according to claim 18, wherein the 2.5V I/O device has a second single-layer antenna ratio of smaller than or equal to 600 (Matsunaga discloses In the memory 57, 59 and I/O circuit 63, 65, the maximum value Rmax1 of antenna ratio is 500 times, [0083]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571) 270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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