DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 9-10, and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over MA et al. (US 20170345824 A1, hereinafter Ma) in view of Seo et. Al (US 20080064206 A1, hereinafter Seo)
With regards to claim 7, Ma discloses a memory device, (FIG. 2A) comprising:
a substrate, (substrate 100) having a plurality of active areas; (source/drain region 50)
a plurality of bit-line structures, (bit lines BL) disposed on the substrate in parallel; (see FIG. 2A)
a plurality of conductive plugs, (upper contact plugs 296) respectively disposed aside the plurality of bit-line structures, and electrically connected to the plurality of active areas; (see FIG. 2A) and
a plurality of conductive pads, (lower pad 290) vertically disposed between the plurality of conductive plugs and the plurality of active areas, wherein a perimeter of one of the plurality of conductive plugs falls within a perimeter of a corresponding conductive pad in a top view. (See FIG. 2A, where the plug 296 has a perimeter that “falls within “ the perimeter is on the layer 290)
However, Ma does not explicitly teach wherein a perimeter of one of the plurality of conductive plugs falls entirely within a perimeter of a corresponding conductive pad in a top view.
Seo teaches wherein a perimeter of one of the plurality of conductive plugs (plug 127) falls entirely within a perimeter of a corresponding conductive pad (pad 106) in a top view.
It would have been obvious to one of ordinary skill in the art to modify the device of Seo to have the contained perimeter of Seo, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that QQQ.
With regards to claim 9, Ma in view of Seo teaches the memory device according to claim 7, wherein the plurality of conductive pads are embedded in the substrate, (see FIG. 2A, showing the embedding)
However, Ma does not explicitly teach a top surface of the plurality of conductive pads is level with a top surface of the plurality of active areas.
It should be noted that the courts have found that the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice (See MPEP 2144.04 VI. C. rearrangement of parts) In the instant case, the placement of the conductive pads would be an obvious matter of design choice.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Ma to have the placement of the layers as recited above.
With regards to claim 10, Ma in view of Seo teaches the memory device according to claim 7.
Ma further teaches wherein the plurality of conductive pads are in direct contact with the plurality of active areas. (See FIG. 2A, showing the direct contact)
With regards to claim 13, Ma in view of Seo teaches the memory device according to claim 7.
Ma further teaches further comprising a bit- line contact (node contact 215) disposed between each active area and a corresponding bit-line structure. (See FIG. 2A)
With regards to claim 14, Ma in view of Seo teaches the memory device according to claim 13.
However, Ma does not explicitly teach wherein a bottom surface of the plurality of conductive pads is level with a bottom surface of the bit-line contact.
It should be noted that the courts have found that the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice (See MPEP 2144.04 VI. C. rearrangement of parts) In the instant case, the placement of the conductive pads would be an obvious matter of design choice.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Ma to have the placement of the layers as recited above.
With regards to claim 15, Ma in view of Seo teaches the memory device according to claim 7.
Ma further teaches wherein the plurality of conductive pads are respectively disposed beside the plurality of bit-line structures to form a conductive array. (see FIG. 1A-2A, showing the conductive array)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over MA et al. (US 20170345824 A1, hereinafter Ma) in view of in view of Seo et. Al (US 20080064206 A1, hereinafter Seo), as applied to claim 7, and further in view of Chen et. Al (US 20210082741 A1, hereinafter Chen)
With regards to claim 8, Ma in view of Seo teaches the memory device according to claim 7.
Ma further teaches further comprising:
a liner layer (spacer 250) disposed between the plurality of conductive plugs and the plurality of bit- line structures, (see FIG. 2A, showing the placement and the contact with the upper surface of the plug 290)
However, Ma does not explicitly teach wherein the liner layer has a bottom surface in contact with a portion of a top surface of the plurality of conductive pads.
Chen teaches wherein the liner layer (spacers AG and 112) has a bottom surface (bottom surface of spacer AG) in contact with a portion of a top surface of the plurality of conductive pads. (pad 324, see at least FIG. 6J)
It would have been obvious to one of ordinary skill in the art to modify the device of Ma to have the bottom contact of the spacers of Chen, as both references are in the same field of endeavor.
It should be noted that the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. (See MPEP 2144.04 VI. B)
In the instant case, there would be no new unexpected result from modifying the s
With regards to claim 11, Ma in view of Seo and Chen teaches the memory device according to claim 8.
Ma further teaches wherein a material of the liner layer comprises a dielectric material. (Paragraph [0024]: “For example, the spacers 250 may include one or more, in some embodiments, at least two, of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.”)
With regards to claim 12, Ma in view of Seo and Chen teaches the memory device according to claim 8.
Ma further teaches wherein the liner layer electrically isolates the plurality of conductive plugs from the plurality of bit-line structures. (see FIG. 2A, showing the isolation)
Response to Arguments
Applicant's arguments filed 09/05/2025 have been fully considered but they are moot, as examiner relies on Seo to teach the current limitations as recited above.
Therefore, claims 7-8 are rejected, and claims 9-15 are rejected for at least their dependencies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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