DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 2/11/2026 is acknowledged.
Applicant amended claims 1, 3, 4, 22, 23, 32, and 36; and cancelled claims 2 and 34.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6-8, 17, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Moroz et al. (US 2019/0348541) (hereafter Moroz), in view of Dyer et al. (US 2007/0298552) (hereafter Dyer).
Regarding claim 1, Moroz discloses a semiconductor device comprising:
a nanosheet stack layer 508 (Fig. 5, paragraph 0052) on a substrate 520 (Fig. 5, paragraph 0052) comprising a plurality of nanosheets 508 (Fig. 5) spaced apart from each other in a vertical direction (vertical direction in Fig. 5) relative to the substrate 520 (Fig. 5), wherein
each nanosheet of the plurality of nanosheets 508 (Fig. 5) comprises an upper surface and a lower surface (see Fig. 4, wherein left upper surface of nanosheets in column 414 is opposite to right lower surface of nanosheets in column 414) opposite to each other;
at least one nanosheet 508 (Fig. 5) of the plurality of nanosheets 508 (Fig. 5) comprises a first portion (top portion of 508 in Fig. 5) in a first orientation (see paragraph 0049, wherein “standard {100} top and bottom surfaces”), and an upper surface and a lower surface (see Figs. 4 and 5, wherein left upper and right lower surfaces of nanosheets in column 414 (Fig. 4) is not parallel to the horizontal surface of the substrate 520 (Fig. 5)) of the first portion (top portion of 508 in Fig. 5) are in the first orientation (see paragraph 0049, wherein “standard {100} top and bottom surfaces”) and have a non-zero angle with a horizontal direction of the substrate 520 (Fig. 5).
wherein an orthographic projection of the upper surface (left upper surface of nanosheets in column 414 in Fig. 4) of the first portion on a surface of the substrate 520 (Fig. 5) overlaps with an orthographic projection of the lower surface (right lower surface of nanosheets in column 414 in Fig. 4) of the first portion on the surface of the substrate 520 (Fig. 5).
Moroz does not disclose the at least one nanosheet further comprises a second portion in a second orientation different from the first orientation.
Dyer discloses the at least one nanosheet 20’ (Fig. 4, paragraph 0054) further comprises a second portion (bottom portion of 20’ in Fig. 4, paragraph 0054) in a second orientation (see paragraph 0054, wherein “the bottom surface 20A' of the 3D semiconductor structure 20' is oriented along one of the {100} surfaces of silicon”) different from the first orientation (see paragraph 0054, wherein “the additional surfaces 20B' are oriented along the {110} surfaces of silicon”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz to form the at least one nanosheet further comprises a second portion in a second orientation different from the first orientation, as taught by Dyer, since providing 3D semiconductor device structures (Dyer, paragraph 0006) that are located over the same substrate but have different surface orientations (i.e., hybrid surface orientations), which provide optimal carrier mobility in respective 3D FET devices.
Regarding claim 3, Moroz further discloses the semiconductor device according to claim 1, wherein the horizontal surface of the substrate 520 (Fig. 5) is one of {100} crystal plane families (see paragraph 0046, wherein “{100} wafers family of planes”).
Moroz does not disclose the upper surface and the lower surface of the first portion are one of {110} crystal plane families; or
the horizontal surface of the substrate is one of {110} crystal plane families, and the upper surface and the lower surface of the first portion are one of {100} crystal plane families.
Dyer discloses the upper surface (left upper 20B' in Fig. 4) and the lower surface (right lower 20B' in Fig. 4) of the first portion (top portion of 20’ in Fig. 4, paragraph 0054) are one of {110} crystal plane families (see paragraph 0054, wherein “the additional surfaces 20B' are oriented along the {110} surfaces of silicon”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz to form the at least one of the upper surface or the lower surface of the first portion is one of {110} crystal plane families, as taught by Dyer, since providing 3D semiconductor device structures (Dyer, paragraph 0006) that are located over the same substrate but have different surface orientations (i.e., hybrid surface orientations), which provide optimal carrier mobility in respective 3D FET devices.
Regarding claim 4, Moroz further discloses the semiconductor device according to claim 1, wherein the horizontal surface of the substrate 520 (Fig. 5) is one of {100} crystal plane families (see paragraph 0046, wherein “{100} wafers family of planes”).
Moroz does not disclose the upper surface and the lower surface of the first portion are one of {110} crystal plane families, and an upper surface or a lower surface of the second portion are one of the {100} crystal plane families; or
the horizontal surface of the substrate is one of {110} crystal plane families, the upper surface and the lower surface of the first portion are one of {110} crystal plane families, and an upper surface and a lower surface of the second portion are one of the {110} crystal plane families.
Dyer discloses the upper surface (left upper 20B' in Fig. 4) and the lower surface (right lower 20B' in Fig. 4) of the first portion (top portion of 20’ in Fig. 4) are one of {110} crystal plane families (see paragraph 0054, wherein “the additional surfaces 20B' are oriented along the {110} surfaces of silicon”), and an upper surface or a lower surface (bottom surface of 20A’ in Fig. 4) of the second portion (bottom portion of 20’ in Fig. 4, paragraph 0054) are one of the {100} crystal plane families (see paragraph 0054, wherein “the bottom surface 20A' of the 3D semiconductor structure 20' is oriented along one of the {100} surfaces of silicon”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz to form the upper surface and the lower surface of the first portion are one of {110} crystal plane families, and an upper surface or a lower surface of the second portion are one of the {100} crystal plane families, as taught by Dyer, since providing 3D semiconductor device structures (Dyer, paragraph 0006) that are located over the same substrate but have different surface orientations (i.e., hybrid surface orientations), which provide optimal carrier mobility in respective 3D FET devices.
Regarding claim 6, Moroz further discloses the semiconductor device according to claim 1, wherein the at least one nanosheet 508 (Fig. 5, paragraph 0052) of the plurality of nanosheets 508 (Fig. 5) is in a shape of a broken line (see Fig. 5, wherein 508 are spaced apart) with one or more inflection points (see Fig. 5, wherein 508 has curved surfaces).
Regarding claim 7, Moroz further discloses the semiconductor device according to claim 1, further comprising: source/drain portions (630 and 632 in Fig. 6, paragraph 0054) on the substrate 520 (Fig. 6) located on two opposite sides of the nanosheet stack layer 620 (Fig. 6, paragraph 0054) in a first direction (horizontal direction in Fig. 6) and connected with the nanosheets 620 (Fig. 6) in the nanosheet stack layer 620 (Fig. 6); and a gate stack 622 (Fig. 6, paragraph 0054) on the substrate 520 (Fig. 6) extending in a second direction (stacking direction in Fig. 6) and overlapping the nanosheets 620 (Fig. 6), wherein the second direction (stacking direction in Fig. 6) intersects the first direction (horizontal direction in Fig. 6).
Regarding claim 8, Moroz further discloses the semiconductor device according to claim 7, wherein the gate stack 622 (Fig. 6, paragraph 0054) is disposed between the nanosheet stack layer 620 (Fig. 6) and the substrate 520 (Fig. 6), between the nanosheets 620 (Fig. 6) in the nanosheet stack layer 620 (Fig. 6), and above the nanosheet stack layer 620 (Fig. 6).
Regarding claim 17, Moroz further discloses the semiconductor device according to claim 7, wherein a plurality of the semiconductor devices (502 and 504 in Fig. 5, paragraph 0052) are provided on the substrate 520 (Fig. 5), and semiconductor devices (502 and 504 in Fig. 5) adjacent in the first direction (horizontal direction in Fig. 5) in the plurality of the semiconductor devices (502 and 504 in Fig. 5) are electrically isolated from each other by an isolation portion 518 (Fig. 5, paragraph 0052), wherein the isolation portion 518 (Fig. 5) extends in the second direction (stacking direction in Fig. 5).
Regarding claim 40, Moroz discloses an electronic apparatus comprising the semiconductor device according to claim 1, wherein the electronic apparatus (see paragraph 0082, wherein “The computer system may be a server computer, a client computer, a workstation, a mainframe, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a smartphone, a web appliance, a rack-mounted “blade”, a kiosk, a television, a game station, a network router, switch or bridge, or any data processing machine capable of executing instructions”) comprises a smartphone, a computer, a tablet computer, an artificial intelligence apparatus, a wearable apparatus, or a mobile power supply.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Moroz in view of Dyer as applied to claim 1 above, and further in view of Chiang et al. (US 2020/0058653) (hereafter Chiang).
Regarding claim 5, Moroz in view of Dyer discloses the semiconductor device according to claim 1, however Moroz and Dyer do not disclose a spacing distance between adjacent nanosheets of the plurality of nanosheets is substantially uniform.
Chiang discloses a spacing distance (see 208 between 206 in Fig. 12 and see paragraph 0023, wherein “the epitaxial layers 208 of the stack are substantially uniform in thickness”) between adjacent nanosheets 206 (Fig. 17, paragraph 0037) of the plurality of nanosheets is substantially uniform.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form a spacing distance between adjacent nanosheets of the plurality of nanosheets is substantially uniform, as taught by Chiang, since the epitaxial layers 206 (Chiang, Fig. 17, paragraph 0023) serve as nanowire channels and epitaxial layers 208 (Chiang, Fig. 17, paragraph 0023) serve to define a gap distance between adjacent nanowire channels; in a subsequently-formed p-type FinFET, the epitaxial layers 206 and 208 (Chiang, Fig. 17, paragraph 0023) jointly serve as channels, with their respective thicknesses chosen based on device performance considerations.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Moroz in view of Dyer as applied to claim 8 above, and further in view of Xie et al. (US 9984936 B1) (hereafter Xie).
Regarding claim 9, Moroz in view of Dyer discloses the semiconductor device according to claim 8, however Moroz and Dyer do not disclose a dielectric layer disposed between the gate stack and the substrate.
Xie discloses a dielectric layer (128 and 129 in Fig. 14, Col. 8, Lines 57-58) disposed between the gate stack 146 (Fig. 14) and the substrate 102 (Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form a dielectric layer disposed between the gate stack and the substrate, as taught by Xie, since forming (Xie, first paragraph in Col. 2) an isolated nano-sheet transistor device and the resulting novel device that may avoid, or at least reduce, the effects of parasitic capacitor (Xie, Bridging paragraph from Col. 1 to Col. 2) that would charge and discharge every time the gate structure is energized.
Regarding claim 10, Moroz in view of Dyer and Xie discloses the semiconductor device according to claim 9, however Moroz and Dyer do not disclose the dielectric layer comprises an air gap.
Xie discloses the dielectric layer (128 and 129 in Fig. 14, Col. 8, Lines 57-58) comprises an air gap 129 (Fig. 14, Col. 8, Line 58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form the dielectric layer comprises an air gap, as taught by Xie, since forming (Xie, first paragraph in Col. 2) an isolated nano-sheet transistor device and the resulting novel device that may avoid, or at least reduce, the effects of parasitic capacitor (Xie, Bridging paragraph from Col. 1 to Col. 2) that would charge and discharge every time the gate structure is energized.
Claims 11 are rejected under 35 U.S.C. 103 as being unpatentable over Moroz in view of Dyer as applied to claim 8 above, and further in view of Lee et al. (US 20190341450) (hereafter Lee).
Regarding claim 11, Moroz in view of Dyer discloses the semiconductor device according to claim 8, however Moroz and Dyer do not disclose a gate spacer disposed on a sidewall of the gate stack, wherein the gate spacer comprises a first portion above a respective nanosheet and a second portion below the respective nanosheet.
Lee discloses a gate spacer (1102B and 1102C in Fig. 19, paragraph 0050) disposed on a sidewall of the gate stack (not shown in Fig. 19 but see 304 (Fig. 19) is replaced with “metal gate” (paragraph 0063)), wherein the gate spacer (1102B and 1102C in Fig. 19) comprises a first portion 1102C (Fig. 19, paragraph 0050) above a respective nanosheet 126A (Fig. 19, paragraph 0050) and a second portion 1102B (Fig. 19, paragraph 0050) below the respective nanosheet 126A (Fig. 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form a gate spacer disposed on a sidewall of the gate stack, wherein the gate spacer comprises a first portion above a respective nanosheet and a second portion below the respective nanosheet, as taught by Lee, since the inner spacers (Lee, paragraph 0035) protect the channel nanosheets from the source and drain regions, and also provide electric isolation and support between the channels.
Regarding claim 12, Moroz in view of Dyer and Lee discloses the semiconductor device according to claim 11, however Moroz and Dyer do not disclose the first portion of the gate spacer has a thickness substantially the same as a thickness of the second portion of the gate spacer.
Lee discloses the first portion 1102C (Fig. 19, paragraph 0050) of the gate spacer (1102B and 1102C in Fig. 19, paragraph 0050) has a thickness (a3 in Fig. 19, paragraph 0057) substantially the same as a thickness of the second portion 1102B (Fig. 19, paragraph 0050) of the gate spacer (1102B and 1102C in Fig. 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form the first portion of the gate spacer has a thickness substantially the same as a thickness of the second portion of the gate spacer, as taught by Lee, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 13, Moroz in view of Dyer and Lee discloses the semiconductor device according to claim 11, however Moroz and Dyer do not disclose an inner sidewall of the first portion of the gate spacer and an inner sidewall of the second portion of the gate spacer are substantially aligned in the vertical direction.
Lee discloses an inner sidewall of the first portion 1102C (Fig. 19, paragraph 0050) of the gate spacer (1102B and 1102C in Fig. 19, paragraph 0050) and an inner sidewall of the second portion 1102B (Fig. 19, paragraph 0050) of the gate spacer are substantially aligned in the vertical direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form an inner sidewall of the first portion of the gate spacer and an inner sidewall of the second portion of the gate spacer are substantially aligned in the vertical direction, as taught by Lee, since the inner spacers (Lee, paragraph 0035) protect the channel nanosheets from the source and drain regions, and also provide electric isolation and support between the channels.
Regarding claim 14, Moroz in view of Dyer and Lee discloses the semiconductor device according to claim 11, however Moroz and Dyer do not disclose an outer sidewall of the gate spacer is substantially aligned with an outer sidewall of the respective nanosheet in the nanosheet stack layer in the vertical direction.
Lee discloses an outer sidewall of the gate spacer (1102B and 1102C in Fig. 19, paragraph 0050) is substantially aligned with an outer sidewall of the respective nanosheet 126A (Fig. 19, paragraph 0050) in the nanosheet stack layer in the vertical direction (vertical direction in Fig. 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form an outer sidewall of the gate spacer is substantially aligned with an outer sidewall of the respective nanosheet in the nanosheet stack layer in the vertical direction, as taught by Lee, since the inner spacers (Lee, paragraph 0035) protect the channel nanosheets from the source and drain regions, and also provide electric isolation and support between the channels.
Claims 20 are rejected under 35 U.S.C. 103 as being unpatentable over Moroz in view of Dyer as applied to claim 17 above, and further in view of Mehandru et al. (US 2020/0006559) (hereafter Mehandru).
Regarding claim 20, Moroz in view of Dyer discloses the semiconductor device according to claim 17, however Moroz and Dyer do not disclose the isolation portion contains a multilayer dielectric material.
Mehandru discloses the isolation portion (380 and 315 in Fig. 13A, paragraph 0073) contains a multilayer dielectric material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Moroz in view of Dyer to form the isolation portion contains a multilayer dielectric material, as taught by Mehandru, since the isolation scheme (Mehandru, paragraph 0030) includes changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices.
Claims 22-24, and 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US 2020/0058653) (hereafter Chiang), in view of Moroz et al. (US 2019/0348541) (hereafter Moroz), in further view of Rodder et al. (US 2018/0114727) (hereafter Rodder).
Regarding claim 22, Chiang discloses a semiconductor device, comprising:
a first device (“transistors” (see paragraph 0025) with 284 in Fig. 17) and a second device (“transistors” (see paragraph 0025) with 286 in Fig. 17) on a substrate 202 (Fig. 17, paragraph 0026), wherein the first device (“transistors” (see paragraph 0025) with 284 in Fig. 17) comprises a plurality of first nanosheets (206 of 210 in Fig. 17, paragraph 0037) stacked and spaced apart from each other in a vertical direction (vertical direction in Fig. 17) relative to the substrate 202 (Fig. 17), the second device (“transistors” (see paragraph 0025) with 286 in Fig. 17) comprises a plurality of second nanosheets (206 of 212 in Fig. 17, paragraph 0037) stacked and spaced apart from each other in the vertical direction (vertical direction in Fig. 17) relative to the substrate 202 (Fig. 17), each nanosheet of the plurality of first nanosheets (206 of 210 in Fig. 17) comprises an upper surface (upper surface of 206 of 210 in Fig. 17) and a lower surface (lower surface of 206 of 210 in Fig. 17) opposite to each other, and each nanosheet of the plurality of second nanosheets (206 of 212 in Fig. 17) comprises an upper surface (upper surface of 206 of 212 in Fig. 17) and a lower surface (lower surface of 206 of 212 in Fig. 17) opposite to each other.
Chiang does not disclose at least one of the first nanosheets comprises a first portion in a first orientation, an upper surface and a lower surface of the first portion are in the first orientation, and an orthographic projection of the upper surface of the first portion on a surface of the substrate overlaps with an orthographic projection of the lower surface of the first portion on the surface of the substrate.
Moroz discloses at least one of the first nanosheets (508 of 502 in Fig. 5, paragraph 0052) comprises a first portion (508 of 502 in Fig. 5) in a first orientation (see paragraph 0049, wherein “{111} top and bottom surfaces”), an upper surface (upper surface of 508 of 502 in Fig. 5) and a lower surface (lower surface of 508 of 502 in Fig. 5) of the first portion (508 of 502 in Fig. 5) are in the first orientation (see paragraph 0049, wherein “{111} top and bottom surfaces”), and an orthographic projection of the upper surface (upper surface of 508 of 502 in Fig. 5) of the first portion (508 of 502 in Fig. 5) on a surface of the substrate 520 (Fig. 5, paragraph 0052) overlaps with an orthographic projection of the lower surface (lower surface of 508 of 502 in Fig. 5) of the first portion (508 of 502 in Fig. 5) on the surface of the substrate 520 (Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang to form at least one of the first nanosheets comprises a first portion in a first orientation, an upper surface and a lower surface of the first portion are in the first orientation, and an orthographic projection of the upper surface of the first portion on a surface of the substrate overlaps with an orthographic projection of the lower surface of the first portion on the surface of the substrate, as taught by Moroz, since the stability (Moroz , paragraph 0048) of {111} plane in a diamond-cubic crystal lattice is taken advantage of to reduce manufactured nanosheet imperfections.
Chiang and Moroz do not disclose at least one of the second nanosheets comprises a second portion in a second orientation different from the first orientation, and an upper surface and a lower surface of the second portion are in the second orientation.
Rodder discloses at least one of the second nanosheets (right 205 in Fig. 2C, paragraph 0058) comprises a second portion (right 205 in Fig. 2C) in a second orientation (“(100) orientation” in paragraph 0056) different from the first orientation (“(110) orientation” in paragraph 0056), and an upper surface (upper surface of right 205 in Fig. 2C) and a lower surface (lower surface of right 205 in Fig. 2C) of the second portion (right 205 in Fig. 2C) are in the second orientation (see paragraph 0056, wherein “upper and lower surfaces of the conducting channel layers 202 have a (100) orientation”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Moroz to form at least one of the second nanosheets comprises a second portion in a second orientation different from the first orientation, and an upper surface and a lower surface of the second portion are in the second orientation, as taught by Rodder, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing (100) orientation as a second orientation from the listed in Rodder (e.g. (110) orientation or (100) orientation); if this leads to the anticipated success, in the instant case forming a channel layer, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 23, Chiang further discloses the semiconductor device according to claim 22, wherein a horizontal surface of the substrate 202 (Fig. 17) is one of {100} crystal plane families (see paragraph 0046, wherein “{100} wafers family of planes”).
Chiang and Moroz do not disclose the upper surface and the lower surface of the first portion are one of {110} crystal plane families, and the upper surface and the lower surface of the second portion are one of the {100} crystal plane families; or
a horizontal surface of the substrate is one of {110} crystal plane families, the upper surface and the lower surface of the first portion are one of {100} crystal plane families, and the upper surface and the lower surface of the second portion are one of the {110} crystal plane families.
Rodder discloses the upper surface and the lower surface of the first portion (left 205 in Fig. 2C) are one (see paragraph 0056, wherein “the upper and lower surfaces of the conducting channel layers 202 have a (110) orientation”) of {110} crystal plane families (“(110) orientation” in paragraph 0056), and the upper surface and the lower surface of the second portion (right 205 in Fig. 2C) are one (see paragraph 0056, wherein “upper and lower surfaces of the conducting channel layers 202 have a (100) orientation”) of the {100} crystal plane families.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Moroz to form the upper surface and the lower surface of the first portion are one of {110} crystal plane families, and the upper surface and the lower surface of the second portion are one of the {100} crystal plane families, as taught by Rodder, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing (100) orientation as a second orientation from the listed in Rodder (e.g. (110) orientation or (100) orientation); if this leads to the anticipated success, in the instant case forming a channel layer, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 24, Chiang further discloses the semiconductor device according to claim 22, wherein a spacing (see 208 between 206 in Fig. 12 and see paragraph 0023, wherein “the epitaxial layers 208 of the stack are substantially uniform in thickness”) distance between adjacent nanosheets (206 of 210 in Fig. 17) in the first nanosheets is substantially uniform, and a spacing distance (see 208 between 206 in Fig. 12 and see paragraph 0023, wherein “the epitaxial layers 208 of the stack are substantially uniform in thickness”) between adjacent nanosheets in the second nanosheets (206 of 212 in Fig. 17) is substantially uniform wherein the first nanosheet (206 of 210 in Fig. 17) and the second nanosheet (206 of 212 in Fig. 17) that are located at a same level relative to the substrate 202 (Fig. 17) contain substantially a same material (see paragraph 0020, wherein “silicon (Si)”) and have substantially a same thickness (see paragraph 0023, wherein “The epitaxial layers 206 may be substantially uniform in thickness”); wherein a distance between the first nanosheets (206 of 210 in Fig. 17) at adjacent levels relative to the substrate 202 (Fig. 17) is substantially the same as a distance between the second nanosheets (206 of 212 in Fig. 17) at corresponding adjacent levels.
Regarding claim 27, Chiang further discloses the semiconductor device according to claim 22, further comprising: first source/drain portions 254 (Fig. 10A, paragraph 0038) located on two opposite sides of the plurality of first nanosheets 206 (Fig. 10A, paragraph 206) in a first direction (Y direction in Fig. 10A) and connected with the first nanosheets 206 (Fig. 10A);
a first gate stack (290 of 210 in Fig. 17, paragraph 0052) on the substrate 202 (Fig. 17) extending in a second direction (X direction in Fig. 17) and overlapping the first nanosheets (206 of 210 in Fig. 17), wherein the second direction (X direction in Fig. 17) intersects (see XYZ directions in Fig. 4) the first direction (Y direction in Fig. 10A);
second source/drain portions 258 (Fig. 10A, paragraph 0039) located on two opposite sides of the plurality of second nanosheets 206 (Fig. 10B) in the first direction (Y direction in Fig. 10B) and connected with the second nanosheets 206 (Fig. 10B); and
a second gate stack (290 of 212 in Fig. 17, paragraph 0052) on the substrate 202 (Fig. 17) extending in the second direction (X direction in Fig. 17) and overlapping the second nanosheets 206 (Fig. 10B).
Regarding claim 28, Chiang further discloses the semiconductor device according to claim 27, wherein the first gate stack (290 of 210 in Fig. 17) is aligned with the second gate stack (290 of 212 in Fig. 17) in the second direction (X direction in Fig. 17), and the first nanosheet (206 of 210 in Fig. 17) is aligned with the second nanosheet (206 of 212 in Fig. 17) in the second direction (X direction in Fig. 17).
Regarding claim 29, Chiang further discloses the semiconductor device according to claim 28, further comprising: a gate spacer (element number is not shown in Fig. 17 but see 244 in Fig. 15, paragraph 0035) extending continuously on a sidewall of the first gate stack (290 of 210 in Fig. 17), on a sidewall of the second gate stack (290 of 212 in Fig. 17), and between the first gate stack (290 of 210 in Fig. 17) and the second gate stack (290 of 212 in Fig. 17).
Regarding claim 30, Chiang further discloses the semiconductor device according to claim 27, further comprising a dielectric layer 222 (Fig. 17, paragraph 0030) disposed between at least one of the first gate stack (290 of 210 in Fig. 17) and the second gate stack (290 of 212 in Fig. 17) and the substrate 202 (Fig. 17).
Claims 32, 33, 35, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US 2020/0058653) (hereafter Chiang), in view of Moroz et al. (US 2019/0348541) (hereafter Moroz), in further view of Dyer et al. (US 2007/0298552) (hereafter Dyer).
Regarding claim 32, Chiang discloses a method of manufacturing a semiconductor device, comprising:
forming a pattern (vertical portion of 202 in Fig. 5) on a substrate (bottom portion of 202 in Fig. 5, paragraph 0026), wherein the first surface (vertical portion of 202 in Fig. 5) is not parallel to a horizontal surface of the substrate (bottom portion of 202 in Fig. 5, paragraph 0026); and
forming a stack layer 204 (Fig. 5, paragraph 0021) of alternately arranged sacrificial layers 208 (Fig. 5, paragraph 0021) and channel layers 206 (Fig. 5, paragraph 0021) on the substrate (bottom portion of 202 in Fig. 5) having the pattern (vertical portion of 202 in Fig. 5), wherein at least one of the channel layers 206 (Fig. 5) is substantially conformal with the pattern (vertical portion of 202 in Fig. 5), so that an upper surface (upper surface of 206 in Fig. 5) and a lower surface (lower surface of 206 in Fig. 5) of at least a portion of at least one of the channel layers 206 (Fig. 5, paragraph 0021) are in the first orientation (“(110) plane” in paragraph 0021).
Chiang does not disclose an orthographic projection of the upper surface of the at least a portion on the horizontal surface of the substrate overlaps with an orthographic projection of the lower surface of the at least a portion on the horizontal surface of the substrate.
Moroz discloses an orthographic projection of the upper surface (upper surface of 508 of 502 in Fig. 5) of the at least a portion (508 of 502 in Fig. 5, paragraph 0052) on the horizontal surface of the substrate 520 (Fig. 5, paragraph 0052) overlaps with an orthographic projection of the lower surface (lower surface of 508 of 502 in Fig. 5) of the at least a portion on the horizontal surface of the substrate 520 (Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang to form an orthographic projection of the upper surface of the at least a portion on the horizontal surface of the substrate overlaps with an orthographic projection of the lower surface of the at least a portion on the horizontal surface of the substrate, as taught by Moroz, since the stability (Moroz, paragraph 0048) of {111} plane in a diamond-cubic crystal lattice is taken advantage of to reduce manufactured nanosheet imperfections.
Chiang and Moroz do not disclose the pattern comprises at least a first surface in a first orientation, and a second surface having a second orientation different from the first orientation.
Dyer discloses the pattern (20 in Fig. 7, paragraph 0060) comprises at least a first surface 20B (Fig. 7, paragraph 0060) in a first orientation (see paragraph 0060, wherein “{110} planes of silicon”), and a second surface 20A (Fig. 7, paragraph 0060) having a second orientation (see paragraph 0060, wherein “{100} planes of silicon”) different from the first orientation (see paragraph 0060, wherein “{110} planes of silicon”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Moroz to include the pattern comprises at least a first surface in a first orientation, and a second surface having a second orientation different from the first orientation, as taught by Dyer, since providing 3D semiconductor device structures (Dyer, paragraph 0006) that are located over the same substrate but have different surface orientations (i.e., hybrid surface orientations), which provide optimal carrier mobility in respective 3D FET devices.
Regarding claim 33, Chiang further discloses the method according to claim 32, further comprising: patterning (see Fig. 5 and paragraph 0025) the stack layer 204 (Fig. 4) into a stripe 204 (Fig. 5) extending in a first direction (Y direction in Fig. 5); forming a sacrificial gate layer 236 (Fig. 7, paragraph 0034) extending in a second direction (X direction in Fig. 7) on the stack layer (206 and 208 in Fig. 7), wherein the second direction (X direction in Fig. 5) intersects the first direction (Y direction in Fig. 5);
selectively etching (see Fig. 9A and paragraph 0037, wherein “the epitaxial layers 208 are removed from the S/D regions by a selective wet etching process”) the stack layer (206 and 208 in Fig. 8) by using the sacrificial gate layer 236 (Fig. 9A) as a mask;
forming, on two opposite sides of the stack layer (206 and 208 in Fig. 10A) in the first direction (Y direction in Fig. 10A) on the substrate 202 (Fig. 10A), semiconductor layers 254 (Fig. 10A, paragraph 0038) for forming source/drain portions 254 (Fig. 10A); and
replacing the sacrificial gate layer 236 (Fig. 11) and the sacrificial layer 208 (Fig. 11) in the stack layer (206 and 208 in Fig. 11) with a gate stack 290 (Fig. 17, paragraph 0052).
Regarding claim 35, Chiang further discloses the method according to claim 32, wherein the horizontal surface of the substrate 202 (Fig. 4) is one of {100} crystal plane families (“(100) plane” in paragraph 0021).
Chiang and Moroz do not disclose the first orientation is one of {110} crystal plane families; or
the horizontal surface of the substrate is one of {110} crystal plane families, and the first orientation is one of {100} crystal plane families.
Dyer discloses the first orientation (see paragraph 0047, wherein “the bottom surface 20A of the 3D semiconductor structure 20 can be oriented along one of the {110} surfaces of silicon”) is one of {110} crystal plane families.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Moroz to form the first orientation is one of {110} crystal plane families, as taught by Dyer, since providing 3D semiconductor device structures (Dyer, paragraph 0006) that are located over the same substrate but have different surface orientations (i.e., hybrid surface orientations), which provide optimal carrier mobility in respective 3D FET devices.
Regarding claim 36, Chiang further discloses the method according to claim 32, wherein the horizontal surface of the substrate 202 (Fig. 4) is one of {100} crystal plane families (“(100) plane” in paragraph 0021).
Chiang and Moroz do not disclose the first orientation is one of {110} crystal plane families, and the second orientation is one of the {100} crystal plane families; or
the horizontal surface of the substrate is one of {110} crystal plane families, the first orientation is one of {100} crystal plane families, and the second orientation is one of the {110} crystal plane families.
Dyer discloses the first orientation (see paragraph 0047, wherein “the bottom surface 20A of the 3D semiconductor structure 20 can be oriented along one of the {110} surfaces of silicon”) is one of {110} crystal plane families, and the second orientation (see paragraph 0047, wherein “{100} surfaces of silicon”) is one of the {100} crystal plane families
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Moroz to form the first orientation is one of {110} crystal plane families, and the second orientation is one of the {100} crystal plane families, as taught by Dyer, since providing 3D semiconductor device structures (Dyer, paragraph 0006) that are located over the same substrate but have different surface orientations (i.e., hybrid surface orientations), which provide optimal carrier mobility in respective 3D FET devices.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Moroz and Dyer as applied to claim 30 above, and further in view of Xie et al. (US 9984936 B1) (hereafter Xie).
Regarding claim 31, Chiang in view of Moroz and Dyer discloses the semiconductor device according to claim 30, however Chiang, Moroz, and Dyer do not disclose the dielectric layer comprises an air gap.
Xie discloses the dielectric layer (128 and 129 in Fig. 14, Col. 8, Lines 57-58) comprises an air gap 129 (Fig. 14, Col. 8, Line 58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Moroz and Dyer to form the dielectric layer comprises an air gap, as taught by Xie, since forming (Xie, first paragraph in Col. 2) an isolated nano-sheet transistor device and the resulting novel device that may avoid, or at least reduce, the effects of parasitic capacitor (Xie, Bridging paragraph from Col. 1 to Col. 2) charge and discharge.
Allowable Subject Matter
1. Claims 15, 16, 18, 19, 21, and 37-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 15 would be allowable because a closest prior art, Moroz et al. (US 2019/0348541), discloses a plurality of the semiconductor devices (502 and 504 in Fig. 5, paragraph 0052) are provided on the substrate 520 (Fig. 5), and semiconductor devices (502 and 504 in Fig. 5) adjacent in the first direction (horizontal direction in Fig. 5) in the plurality of the semiconductor devices (502 and 504 in Fig. 5) are electrically isolated from each other by an isolation portion 518 (Fig. 5, paragraph 0052) but fails to disclose a range of the isolation portion in the first direction is defined by a dummy gate spacer extending in the second direction. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device comprising: a range of the isolation portion in the first direction is defined by a dummy gate spacer extending in the second direction in combination with other elements of the bases claims 11, 8, 7, and 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claims 16 and 21 depend on claim 15.
In addition, claim 18 would be allowable because a closest prior art, Moroz et al. (US 2019/0348541), discloses the source/drain portion (630 and 632 in Fig. 6, paragraph 0054) extends in the second direction (horizontal direction in Fig. 6); and the semiconductor device further comprises: a gate spacer (“spacers” in paragraph 0059) but fails to disclose the semiconductor device further comprises: a gate spacer located between the gate stack and the source/drain portion and a dummy gate spacer located between the source/drain portion and the isolation portion, wherein the gate spacer has a thickness substantially the same as a thickness of the dummy gate spacer in the first direction. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device comprising: a dummy gate spacer located between the source/drain portion and the isolation portion, wherein the gate spacer has a thickness substantially the same as a thickness of the dummy gate spacer in the first direction in combination with other elements of the base claims 17, 7, and 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claim 19 depends on claim 18.
Moreover, claim 37 would be allowable because a closest prior art, Chiang et al. (US 2020/0058653), discloses forming a pattern (vertical portion of 202 in Fig. 5) on a substrate (bottom portion of 202 in Fig. 5, paragraph 0026), wherein the first surface (vertical portion of 202 in Fig. 5) is not parallel to a horizontal surface of the substrate (bottom portion of 202 in Fig. 5, paragraph 0026) but fails to disclose the forming a pattern comprises: forming a stepped pattern on the substrate by etching a surface of the substrate; and performing an ion etching on the surface of the substrate having the stepped pattern, so as to form an inclined surface on the surface of the substrate. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method of manufacturing a semiconductor device, comprising: the forming a pattern comprises: forming a stepped pattern on the substrate by etching a surface of the substrate; and performing an ion etching on the surface of the substrate having the stepped pattern, so as to form an inclined surface on the surface of the substrate in combination with other elements of the base claim 32. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claim 38 depends on claim 37.
Furthermore, claim 39 would be allowable because a closest prior art, Chiang et al. (US 2020/0058653), discloses forming a position defining layer (bottom portion of 222 in Fig. 6; and see paragraph 0030, wherein “multi-layer structure”) on the substrate 202 (Fig. 6); forming a position maintaining layer (top portion of 222 in Fig. 6) on the position defining layer (bottom portion of 222 in Fig. 6), wherein the pattern (vertical portion of 202 in Fig. 6) is formed on the position maintaining layer (top portion of 222 in Fig. 6), wherein the patterning the stack layer 204 (Fig. 4) into a stripe 204 (Fig. 5) extending in a first direction (Y direction in Fig. 5) comprises: forming a stripe-shaped support portion trench (opening between 204 in Fig. 5) extending in the first direction (Y direction in Fig. 5) in the stack layer 204 (Fig. 5); forming a support portion 244 (Fig. 8, paragraph 0035) for supporting the stack layer (206 and 208 in Fig. 8) in the support portion trench (opening between 210 and 212 in Fig. 8); forming a stripe-shaped isolation trench (opening between 244 in Fig. 8) extending in the first direction (stacking direction in Fig. 8) in the stack layer (206 and 208 in Fig. 8) but fails to teach removing the position maintaining layer through the isolation trench; and at least partially filling, through the isolation trench, a dielectric material in a space left below the stack layer by a removal of the position maintaining layer. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method of manufacturing a semiconductor device, comprising: removing the position maintaining layer through the isolation trench; and at least partially filling, through the isolation trench, a dielectric material in a space left below the stack layer by a removal of the position maintaining layer in combination with other elements of the base claims 33 and 32.
Response to Arguments
1. Applicant's arguments filed 2/11/2026 have been fully considered.
2. Applicant's arguments with respect to claims 1, 3-14, 17, 20, 22-24,27-33, 35-36, and 40 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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