Prosecution Insights
Last updated: May 29, 2026
Application No. 17/999,255

LOW RESISTIVITY CONTACTS AND INTERCONNECTS

Final Rejection §103
Filed
Nov 18, 2022
Priority
May 22, 2020 — provisional 62/704,694 +1 more
Examiner
TRAN, TONY
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lam Research Corporation
OA Round
3 (Final)
70%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
603 granted / 858 resolved
+2.3% vs TC avg
Strong +34% interview lift
Without
With
+34.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
25 currently pending
Career history
919
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
82.7%
+42.7% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
0.5%
-39.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 858 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/09/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-6, 9-16, 20, 22-23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKATSUKI in view of Thombare (Pub. No.: US 2018/0294187). Re claim 1, TAKATSUKI teaches a method comprising: providing a feature on a substrate (101), the feature comprising a metal surface (102) having a layer of metal oxide (102a, FIG. 5A, ¶ [0048]) formed thereon and a dielectric surface; and exposing the feature to a metal halide (“a chemical etching is promoted by using at least one of the WF6, WCl5, WCl6”, FIG. 5B, [0050]) to remove the layer of metal oxide (102a) from the metal surface (102) wherein exposing the feature to a metal halide [0060] to remove the layer of metal oxide [0059] from the metal surface comprises exposing the feature to a plurality of cycles (ALD, [0079]) without an intervening reducing agent pulse (note that “.The step of removing the tungsten oxide film 102a is a chemical reaction-based etching process. For example, when the WF.sub.6 gas is supplied as a halogen-containing gas”, ¶ [0067]) TAKATSUKI fails to teach wherein each cycle comprises a dose of a metal halide followed by a pulse of an inert gas. Thombare teaches wherein exposing the feature to a metal halide to remove the layer of metal oxide (“Pulse of Mo-containing precursor with or without H.sub.2 in background” of ¶ [0058] between ¶ [0058]-[0060] processes, note that the Mo-containing precursor is a Cl-containing precursor such as MoOCl.sub.4”, [0066], processes 457 to 458 of FIG. 4B) from the metal surface comprises exposing the feature to a plurality of cycles, wherein each cycle comprises a dose of a metal halide followed by a pulse of an inert gas (‘Argon purge”, [0059]). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing high resistivity for thinner films as taught by Thombare, [0003]. Re claim 2, in the combination, TAKATSUKI teaches the method of claim 1, further comprising filling the feature with a conductive material (210, FIG. 5C, [0074]). Re claim 3, in the combination, TAKATSUKI teaches the method of claim 2, wherein the conductive material (210, FIG. 5C) directly contacts the metal surface (102) and the dielectric surface (110) without an interposed layer. Re claim 4, in the combination, Thombare teaches the method of claim 2, wherein filling the feature with a conductive material comprises depositing a nucleation layer of the conductive material prior to depositing bulk conductive material [0088]. Re claim 5, in the combination, TAKATSUKI teaches the method of claim 2, wherein filling the feature with a conductive material comprises depositing bulk conductive material without depositing a nucleation layer (from the bottom up to form 210, [0074]). Re claim 6, in the combination, TAKATSUKI teaches the method of claim 1, wherein filling the feature comprises an atomic layer deposition or chemical vapor deposition process, including plasma enhanced or thermal processes, to deposit bulk conductive material [0079]. Re claim 9, in the combination, Thombare teaches the method of any of claim 2, wherein exposing the feature to the metal halide and filling the feature with a conductive material are performed in the same chamber (a single deposition chamber, [0088]-[0089]). Re claim 10, in the combination, Thombare teaches the method of claim 2, wherein exposing the feature to the metal halide and filling the feature with a conductive material are performed in different stations of the same chamber (“various steps for the nucleation process are performed at two different stations of a deposition chamber”, [0088]-[0089]). Re claim 11, in the combination, TAKATSUKI teaches the method of any of claim 2, wherein exposing the feature to the metal halide and filling the feature with a conductive material are performed in different chambers (swapping among chambers 11 to 14 as shown in FIG. 1, [0021]). Re claim 12, in the combination, TAKATSUKI teaches the method of claim 1, wherein the conductive material is selected from molybdenum (Mo), ruthenium (Ru), tungsten (W), iridium (ir), chromium (Cr), cobalt (Co), and titanium nitride (TiN) (210, FIG. 5C, [0074]). Re claim 13, in the combination, Thombare teaches the method of claim 1, wherein the metal surface is a one of a titanium nitride (TiN) surface, a molybdenum nitride (MoNx) surface, a tungsten nitride (WN) surface, a tungsten carbon nitride (WCxNy) surface, a tungsten carbide (WCx) surface, a titanium aluminum carbide (TiAlxCy) surface, or a tantalum nitride (TaN) surface (106/206, FIGS. 1A/2, [0020]/[0023]). Re claim 14, in the combination, TAKATSUKI teaches the method of any of claim 1 wherein the metal of the metal halide is one of Mo, W, Cr, Ti, Ta, and vanadium (V) [0094]. Re claim 15, in the combination, TAKATSUKI teaches the method of any of claim 1 wherein the metal halide is one of tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), tungsten pentachloride (WCl5), tungsten hexabromide (WBr6) [0094]. Re claim 16, in the combination, Thombare teaches the method of any of claim 1 wherein the metal halide is one of molybdenum hexafluoride (MoF6) and molybdenum pentachloride (MoCl5) [0004]. Re claim 20, in the combination, TAKATSUKI teaches the method of claim 1, further comprising performing a reducing treatment (with H2, [0068) to remove residual halogen (SOCl2) after removing the layer of metal oxide. Re claim 22, in the combination, TAKATSUKI teaches the method of claim 2, wherein the plurality of cycles is at least 20 cycles (in order to achieve a desired thickness of step 462 of FIG. 4B). Re claim 23, in the combination, TAKATSUKI teaches the method of claim 2, wherein the bulk conductive layer is deposited using the metal halide (WF6, [0067]). Re claim 24, in the combination, TAKATSUKI teaches a method comprising: providing a feature on a substrate, the feature comprising a metal surface (102) having a layer of metal oxide (102a) formed thereon and a dielectric surface (110); and exposing the feature to a metal halide to remove the layer of metal oxide from the metal surface (FIG. 5A → 5B), wherein exposing the feature to a metal halide to remove the layer of metal oxide from the metal surface comprises exposing the feature to a plurality of cycles, wherein each cycle comprises a dose of pulse WCl5 ([0058], note that this is performed under the ALD process, [0079]) without an intervening reducing agent pulse (note that “The step of removing the tungsten oxide film 102a is a chemical reaction-based etching process. For example, when the WF.sub.6 gas is supplied as a halogen-containing gas”, ¶ [0067]), and wherein the bulk conductive layer is deposited using a ruthenium precursor and a reducing agent (of carbon, [0075]). TAKATSUKI fails to teach wherein each cycle comprises a dose of a MoCl5 followed by a pulse of an inert gas and wherein the bulk conductive layer is deposited using a molybdenum precursor. Thombare teaches wherein exposing the feature to a metal halide to remove the layer of metal oxide (“Pulse of Mo-containing precursor with or without H.sub.2 in background” of ¶ [0058] between ¶ [0058]-[0060] processes, note that the Mo-containing precursor is a Cl-containing precursor such as MoOCl.sub.4”, [0066], processes 457 to 458 of FIG. 4B) from the metal surface comprises exposing the feature to a plurality of cycles, wherein each cycle comprises a dose of a metal halide followed by a pulse of an inert gas (‘Argon purge”, [0059]) and wherein the bulk conductive layer is deposited using a molybdenum precursor (456, FIG. 4B). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing high resistivity for thinner films as taught by Thombare, [0003]. Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKATSUKI. Re claim 17/18/19, TAKATSUKI teaches all the limitation of claim 1 and wherein exposing the feature to a metal halide to remove the layer of metal oxide (102a, FIGS. 5A → 5B, [0093]) from the metal surface comprises exposing the feature to a plurality of cycles (ALD process, [0092]). TAKATSUKI fails to teach the limitation of claim 17/18/19. However, TAKATSUKI teaches wherein the metal halide is one of niobium pentachloride (NbCl5) and niobium pentabromide (NbBr5) (claim 17); wherein the metal halide is one of tantalum pentafluoride (TaF5) and tantalum pentachloride (TaCl5) (claim 18); and wherein the metal halide is one of vanadium pentafluoride (VF5), chromium pentafluoride (CrF5), and titanium tetrachloride (TiCl4) (claim 20) (“The tungsten oxide film is an example of the metal oxide film. In this experiment, ClF3, WCl5, and WCl6 gases were used as the other halogen gases”, FIG. 2, ¶ [0045]). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of effecting remove the oxide material using the halogen containing gas as taught by TAKATSUKI, Abstract. Moreover, TAKATSUKI does not specifically disclose the specific material as teaching in claim 17-19. However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416. Claim(s) 13, 5-6, 11-12, 14-16, 20 and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKATSUKI in view of Mullick (Pub. No.: US 2019/0189456). Re claim 1, TAKATSUKI teaches a method comprising: providing a feature on a substrate (101), the feature comprising a metal surface (102) having a layer of metal oxide (102a, FIG. 5A, ¶ [0048]) formed thereon and a dielectric surface; and exposing the feature to a metal halide (“a chemical etching is promoted by using at least one of the WF6, WCl5, WCl6”, FIG. 5B, [0050]) to remove the layer of metal oxide (102a) from the metal surface (102) wherein exposing the feature to a metal halide [0060] to remove the layer of metal oxide [0059] from the metal surface comprises exposing the feature to a plurality of cycles (ALD, [0079]) without an intervening reducing agent pulse (note that “.The step of removing the tungsten oxide film 102a is a chemical reaction-based etching process. For example, when the WF.sub.6 gas is supplied as a halogen-containing gas”, ¶ [0067]) TAKATSUKI fails to teach wherein each cycle comprises a dose of a metal halide followed by a pulse of an inert gas. Mullick teaches wherein exposing the feature to a metal halide ([0027]-[0028]) to remove the layer of metal oxide (130, [0020]) from the metal surface comprises exposing the feature to a plurality of cycles, wherein each cycle comprises a dose of a metal halide followed by a pulse of an inert gas (“The metal halide and/or the reductant may be exposed to the substrate with a carrier gas or diluent gas. Suitable carrier or diluent gases include, without limitation, Ar, N.sub.2, He, Ne, Kr, Xe and mixtures thereof”, [0031], note that the reductant is used to etch residue 140, [0030]). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of etching oxidized metal films that provide less etch residue as taught by Mullick, [0002]. Re claim 2, in the combination, TAKATSUKI teaches the method of claim 1, further comprising filling the feature with a conductive material (210, FIG. 5C, [0074]). Re claim 3, in the combination, TAKATSUKI teaches the method of claim 2, wherein the conductive material (210, FIG. 5C) directly contacts the metal surface (102) and the dielectric surface (110) without an interposed layer. Re claim 5, in the combination, TAKATSUKI teaches the method of claim 2, wherein filling the feature with a conductive material comprises depositing bulk conductive material without depositing a nucleation layer (from the bottom up to form 210, [0074]). Re claim 6, in the combination, TAKATSUKI teaches the method of claim 1, wherein filling the feature comprises an atomic layer deposition or chemical vapor deposition process, including plasma enhanced or thermal processes, to deposit bulk conductive material [0079]. Re claim 11, in the combination, TAKATSUKI teaches the method of any of claim 2, wherein exposing the feature to the metal halide and filling the feature with a conductive material are performed in different chambers (swapping among chambers 11 to 14 as shown in FIG. 1, [0021]). Re claim 12, in the combination, TAKATSUKI teaches the method of claim 1, wherein the conductive material is selected from molybdenum (Mo), ruthenium (Ru), tungsten (W), iridium (ir), chromium (Cr), cobalt (Co), and titanium nitride (TiN) (210, FIG. 5C, [0074]). Re claim 14, in the combination, TAKATSUKI teaches the method of any of claim 1 wherein the metal of the metal halide is one of Mo, W, Cr, Ti, Ta, and vanadium (V) [0094]. Re claim 15, in the combination, TAKATSUKI teaches the method of any of claim 1 wherein the metal halide is one of tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), tungsten pentachloride (WCl5), tungsten hexabromide (WBr6) [0094]. Re claim 16, in the combination, Thombare teaches the method of any of claim 1 wherein the metal halide is one of molybdenum hexafluoride (MoF6) and molybdenum pentachloride (MoCl5) [0004]. Re claim 20, in the combination, TAKATSUKI teaches the method of claim 1, further comprising performing a reducing treatment (with H2, [0068) to remove residual halogen (SOCl2) after removing the layer of metal oxide. Re claim 22, in the combination, TAKATSUKI teaches the method of claim 2, wherein the plurality of cycles is at least 20 cycles (in order to achieve a desired thickness of step 462 of FIG. 4B). Re claim 23, in the combination, TAKATSUKI teaches the method of claim 2, wherein the bulk conductive layer is deposited using the metal halide (WF6, [0067]). Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKATSUKI in view of Mullick and further in view of Thombare. Re claim 24, in the combination, TAKATSUKI teaches a method comprising: providing a feature on a substrate, the feature comprising a metal surface (102) having a layer of metal oxide (102a) formed thereon and a dielectric surface (110); and exposing the feature to a metal halide to remove the layer of metal oxide from the metal surface (FIG. 5A → 5B), wherein exposing the feature to a metal halide to remove the layer of metal oxide from the metal surface comprises exposing the feature to a plurality of cycles, wherein each cycle comprises a dose of pulse WCl5 ([0058], note that this is performed under the ALD process, [0079]) without an intervening reducing agent pulse (note that “The step of removing the tungsten oxide film 102a is a chemical reaction-based etching process. For example, when the WF.sub.6 gas is supplied as a halogen-containing gas”, ¶ [0067]), and wherein the bulk conductive layer is deposited using a ruthenium precursor and a reducing agent (of carbon, [0075]). TAKATSUKI fails to teach wherein each cycle comprises a dose of a MoCl5 followed by a pulse of an inert gas and wherein the bulk conductive layer is deposited using a molybdenum precursor. Mullick teaches wherein exposing the feature to a metal halide ([0027]-[0028]) to remove the layer of metal oxide (130, [0020]) from the metal surface comprises exposing the feature to a plurality of cycles, wherein each cycle comprises a dose of a metal halide followed by a pulse of an inert gas (“The metal halide and/or the reductant may be exposed to the substrate with a carrier gas or diluent gas. Suitable carrier or diluent gases include, without limitation, Ar, N.sub.2, He, Ne, Kr, Xe and mixtures thereof”, [0031], note that the reductant is used to etch residue 140, [0030]). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of etching oxidized metal films that provide less etch residue as taught by Mullick, [0002]. Moreover, TAKATSUKI/Mullick fails to teach wherein the bulk conductive layer is deposited using a molybdenum precursor. Thombare teaches wherein the bulk conductive layer is deposited using a molybdenum precursor (456, FIG. 4B). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing high resistivity for thinner films as taught by Thombare, [0003]. Response to Arguments Applicant's arguments with respect to claims 1-6, 9-20 and 22-24 on the remarks filed on 04/09/2026 have been considered but they are not persuasive because TAKATSUKI teaches exposing the feature to a metal halide (“a chemical etching is promoted by using at least one of the WF6, WCl5, WCl6”, FIG. 5B, [0050]) to remove the layer of metal oxide (102a) from the metal surface (102) wherein exposing the feature to a metal halide [0060] to remove the layer of metal oxide [0059] from the metal surface comprises exposing the feature to a plurality of cycles (ALD, [0079]) without an intervening reducing agent pulse (note that “.The step of removing the tungsten oxide film 102a is a chemical reaction-based etching process. For example, when the WF.sub.6 gas is supplied as a halogen-containing gas”, ¶ [0067]). Furthermore, it is also subject under the new ground of rejection per TAKATSUKI in view of Mullick. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY TRAN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Nov 18, 2022
Application Filed
Jul 29, 2025
Non-Final Rejection mailed — §103
Oct 29, 2025
Response Filed
Dec 09, 2025
Final Rejection mailed — §103
Apr 09, 2026
Request for Continued Examination
Apr 15, 2026
Response after Non-Final Action
Apr 27, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

4-5
Expected OA Rounds
70%
Grant Probability
99%
With Interview (+34.0%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 858 resolved cases by this examiner. Grant probability derived from career allowance rate.

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