Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/10/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/10/2026 and is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 8835311 B2; Collins et al.; (hereinafter “Collins”) in view of US20110233778A1; Lee et al.; (hereinafter “Lee”).
Regarding Claim 1 (currently amended), Collins teaches a method of processing semiconductor substrates (col. 1, ln. 17-20), the method comprising:
providing a semiconductor substrate (#202, Figure 2F, substrate) comprising an exposed oxide surface (col. 5, ln. 53-57, silicon oxide layer #210 disposing on surface of #202);
without forming a titanium nitride layer on the semiconductor substrate (col. 1, ln. 45-60, the adhesion layer between the tungsten nitride barrier and the substrate can alternatively comprise a metal or alloys), depositing a tungsten nitride layer (#240, col. 7, ln. 13-15, tungsten nitride barrier layer), the tungsten nitride layer having a thickness less than about 30 Å (col. 9, ln. 6-13, thickness of #240 is less than thickness of intermediate layer #230, wherein #203 is between 30-50 Å according to col. 6, ln. 57-60).
depositing a tungsten nucleation layer (#250) over the tungsten nitride layer (#240); and
depositing a first amount of bulk tungsten (#260) over the tungsten nucleation layer (#250) and the tungsten nitride layer (#240).
Collins does not explicitly teach depositing the tungsten nitride layer directly on the exposed oxide surface.
However, Lee teaches a comparable method for processing semiconductor substrates ([0007-0008]), comprising depositing the tungsten nitride layer (#110, Figure 1A, tungsten nitride integrated layer) directly on an exposed oxide surface (#108, gate oxide layer).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the invention disclosed by Collins with the teaching of Lee, as it was merely simple substitution of one known element (tungsten nitride layer plus metal nitride adhesion layer on an oxide surface of Collins) for another (tungsten nitride stack on an oxide surface of Lee) in comparable methods to obtain predictable result (protecting underlying region during subsequent bulk metal deposition and improving interlayer adhesion between the oxide layer and the bulk metal, see Lee, [0019]). See MPEP 2143(I)(B).
Regarding Claim 3 (currently amended), Collins in view of Lee teaches the method as described in claim 1, wherein Collins further teaches annealing the tungsten nitride layer prior to depositing a second amount of bulk tungsten over the tungsten nitride layer (col. 5, ln. 30-38, the tungsten nitride layer is annealed to form barrier layer before the deposition of subsequent tungsten layers).
Regarding Claim 16 (currently amended), Collins in view of Lee teaches the method as described in claim 1, wherein Collins further teaches the tungsten nitride layer is deposited directly on the exposed oxide surface of the semiconductor substrate without an intervening titanium nitride layer (see rejection of claim 1, tungsten nitride layer can alternatively form directly on the oxide layer).
Regarding Claim 17, Collins in view of Lee teaches the method as described in claim 16, wherein Collins further teaches the oxide is selected from the group consisting of silicon oxide and aluminum oxide. (col. 5, ln. 53-57, the oxide of dielectric layer #210 comprises silicon oxide).
Regarding Claim 19, Collins in view of Lee teaches the method as described in claim 1, wherein Collins further teaches the tungsten nitride layer is deposited on a partially fabricated semiconductor substrate for forming a tungsten word line (col. 12, ln. 25-28 and ln. 54-56, the tungsten metallization layers form in word/bit-line trenches of the substrate).
Claims 2 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Lee, further in view of US20150179461A1; Bamnolker et al.; (hereafter “Bamnolker”).
Regarding Claim 2 (currently amended), Collins in view of Lee teaches the method of processing semiconductor substrates as described in claim 1.
Collins in view of Lee does not teach the tungsten nucleation layer and the first amount of bulk tungsten are deposited over the tungsten nitride layer without annealing the tungsten nitride layer.
However, Bamnolker teaches a comparable method of processing a semiconductor substrate (Figure 4, [0004-0005]), wherein a tungsten nucleation layer and a bulk tungsten are deposited over a tungsten nitride layer without annealing the tungsten nitride layer ([0088], layers such as nitride layer, which can be either a titanium nitride layer or a tungsten nitride layer according to [0004], and tungsten layers can be deposited without any annealing step).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the invention disclosed by Collins in view of Lee with the teaching of Bamnolker in order to determine the effect of annealing on uniformity of deposited layers according to Bamnolker, [0088].
Regarding Claim 12, Collins in view of Lee teaches the method as described in claim 1.
Collins in view of Lee does not teach the method further comprising annealing the semiconductor substrate at a temperature between about 500°C. and about 800°C.
However, Bamnolker teaches annealing the semiconductor substrate at a temperature between about 500°C. and about 800°C ([0040], to achieve low resistivity, annealing of the substrate is conducted at relative low temperature such as about 500°C).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the invention disclosed by Collins in view of Lee with the teaching of Bamnolker in order to further reduce the film resistivity according to Bamnolker, [0040].
Regarding Claim 13, Collins in view of Lee and Bamnolker teaches the method as described in claim 12.
Collins in view of Lee does not teach the semiconductor substrate is annealed after depositing the tungsten nitride layer and before depositing the tungsten nucleation layer.
However, Bamnolker teaches the semiconductor substrate is annealed after depositing the tungsten nitride layer and before depositing the tungsten nucleation layer ([0080-0081], the substrate with a titanium nitride/tungsten nitride barrier layer, [0004], can be annealed before any tungsten deposition steps which includes the nucleation layer deposition as described in [0053]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the invention disclosed by Collins in view of Lee with the teaching of Bamnolker for the reason set forth in the rejection of claim 12.
Regarding Claim 14, Collins in view of Lee and Bamnolker teaches the method as described in claim 12.
Collins in view of Lee does not teach the semiconductor substrate is annealed after depositing the bulk tungsten.
However, Bamnolker teaches the semiconductor substrate is annealed after depositing the bulk tungsten ([0027], annealing can be performed after deposition of the bulk tungsten).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the invention disclosed by Collins in view of Lee with the teaching of Bamnolker for the reason set forth in the rejection of claim 12.
Regarding Claim 15, Collins in view of Lee and Bamnolker teaches the method as described in claim 12, wherein Collins further teaches the temperature (see rejection of claim 12 for the annealing temperature of the substrate) is less than a temperature at which tungsten nitride decomposes (Collins, col. 1, ln. 51-55, tungsten nitride decomposes at temperature ranging from 700°C to 1000°C).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Lee, and further in view of US7691749B2; Levy et al.; (hereinafter “Levy”).
Regarding Claim 4, Collins in view of Lee teaches the method of processing semiconductor substrates as described in claim 1.
Collins in view of Lee does not explicitly teach the depositing the tungsten nitride layer, the depositing the tungsten nucleation layer, and the depositing the first amount of bulk tungsten are performed without breaking vacuum.
However, Levy teaches a method for depositing tungsten nitride layer on a substrate (col. 2, ln. 18-21), wherein the depositing the tungsten nitride layer, the depositing the tungsten nucleation layer, and the depositing the first amount of bulk tungsten are performed without breaking vacuum. (col. 12, ln. 21-24, the deposition of tungsten nitride layer, tungsten nucleation and tungsten bulk are performed without vacuum break).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the invention disclosed by Collins in view of Lee with the teaching of Levy by known method, as each element merely performs the same function on comparable devices as it does separately (formation of film stack includes sequentially depositing tungsten nitride, nucleation and bulk tungsten on substrate, see Levy, col. 14, ln. 17-30) and yields predictable result. See MPEP 2143(I)(A).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Lee and Levy, and further in view of US20180174901A1; Wang et al.; (hereinafter “Wang”).
Regarding Claim 11, Collins in view of Lee and Levy teaches the method of processing semiconductor substrates as described in claim 4.
Collins in view of Lee and Levy does not explicitly teach the depositing the tungsten nitride layer, the depositing the tungsten nucleation layer, and the depositing the bulk tungsten are performed in the same chamber.
However, Wang teaches a method of processing semiconductor substrate ([0003], features filled in substrate fabrication), the depositing the tungsten nitride layer, the depositing the tungsten nucleation layer, and the depositing the bulk tungsten are performed in the same chamber. (Figure 1 and 10, remote plasma process for the deposition of tungsten nitride liner layer #102 and tungsten nucleation #104 corresponds to block #1001, see [0059] and the selective deposition of bulk tungsten #108 corresponds to block #1003, see [0060], wherein #1001 and #1003 can be performed in the same or different stations of a single chamber according to [0065], see also Figure 11A).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Collins in view of Lee and Levy with the teaching of Wang in order to maintain a same pressure environment for the substrate while being transferred between processing stations without needing to include transfer ports according to Wang, [0069].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Lee, and further in view of Wang.
Regarding Claim 18, Collins in view of Lee teaches the method of processing semiconductor substrates as described in claim 1.
Collins in view of Lee does not explicitly teach the tungsten nitride layer is deposited on a partially fabricated semiconductor substrate for forming a 3D NAND structure.
However, Wang teaches the tungsten nitride layer is deposited on a partially fabricated semiconductor substrate for forming a 3D NAND structure (the deposition of tungsten nitride liner layer #102 on word line structure, see [0029], is used to fill vertical features of vertical NAND/ 3D NAND according to [0058]).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the invention disclosed by Collins in view of Lee with the teaching of Wang, as it was merely simple substitution of one known element for another (tungsten filled word lines on substrate in comparable devices, see Wang, [0058]) to obtain predictable result. See MPEP 2143(I)(B).
Response to Arguments/Amendments
Applicant's amendment to claim 3, page 5 of the remarks, filed 06/10/2026, with respect to 35 U.S.C 112(a) and 35 U.S.C 112(b) rejections of claim 3 have been fully considered and are persuasive. Accordingly, the rejections have been withdrawn.
Applicant's amendment to claim 1 and corresponding arguments, page 6-8 of the remarks, filed 06/10/2026, with respect to 35 U.S.C 102(a)(1) rejection of claim 1 as unpatentable over Collins have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Collins in view of Lee. Lee has been introduced in view of the amendments to claim 1 for teaching at least the limitation: “depositing a tungsten nitride layer directly on the exposed oxide surface” recited in the amended claim 1 (see 35 U.S.C. 103 rejection of claim 1 above).
Additionally, applicant argues on pages 7-8 of the remarks that the advantages of the annealing method of Bamnolker are described only for tungsten nitride (WN) deposited on titanium nitride (TiN). However, examiner respectfully disagrees. Bamnolker does not appear to disclose depositing and annealing a WN layer on a TiN layer, instead paragraph [0039] and Figures 2-4 discloses a method that provides a TiN layer on a dielectric layer (#430) and annealing the TiN layer to lower resistivity before depositing subsequent bulk tungsten. Paragraph [0043] further explicitly discloses that instead of TiN underlayers, annealing of WN underlayers can provide similar advantages.
Conclusion
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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