Prosecution Insights
Last updated: August 14, 2026
Application No. 18/004,594

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE BONDING INTERFACE, AND ASSOCIATED MANUFACTURING METHOD

Non-Final OA §103
Filed
Apr 30, 2024
Priority
Jul 06, 2020 — FR FR2007138 +1 more
Examiner
LOHAKARE, PRATIKSHA JAYANT
Art Unit
Tech Center
Assignee
Soitec
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
77 granted / 94 resolved
+21.9% vs TC avg
Strong +16% interview lift
Without
With
+15.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
25 currently pending
Career history
119
Total Applications
across all art units

Statute-Specific Performance

§103
62.3%
+22.3% vs TC avg
§102
18.6%
-21.4% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 94 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election with traverse of Group I (claims 1-9) in the reply filed on 06/29/2026 is acknowledged . The traversal is on the ground(s) that the present application is a national phase entry under 35 U.S.C. 371 of International Patent Application PCT/FR2021/051023 filed June 8, 2021, designating the United States of America and published as International Patent Publication WO 2022/008809 Al on January 13, 2022, which claims the benefit under Article 8 of the Patent Cooperation Treaty to French Patent Application Serial No. FR2007138, filed July 6, 2020. Furthermore, Applicant respectfully submits that the Examiner has not established that claims 1 and 10 do not involve one or more of the same or corresponding special technical features that define a contribution which each of the claimed inventions, considered as a whole, makes over the prior art. Thus, Applicant respectfully submits that the requirement for restriction is improper, and withdrawal of the restriction requirement and rejoinder and examination of claims 10-20 together with claims 1-9 is respectfully requested. This is found persuasive, therefore the requirement for restriction is withdrawn. Claims 1-20 are pending in this office action. Claim Objections Claim 12 is objected to because of the following informalities: Re claim 12 The limitation in line 2 insert “a buried weakened plane” instead of “a buried weakened plan” Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-6, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton et al (US20150380383A1) in view of Katkar et al (US20230132632A1). Re claim 1 Gondcharton teaches a semiconductor structure, comprising: a working layer (3, fig 4) [0058] made of semiconductor material (silicon substrate) [0058], the working layer extending in a main plane (horizontal); a carrier substrate (1, fig 4) made of semiconductor material (silicon substrate) [0058]; and an interface zone (6, fig 4) [0061] between the working layer (3, fig 4) and the carrier substrate (1, fig 4), the interface zone (6, fog 4) extending parallel to the main plane (horizontal), the interface zone (6, fig 4) comprising electrically conductive nodules (5, fig 4) [0061] comprising a metal material (metal material) [0061] forming an ohmic contact (bonding) [0061] with the working layer (3, fig 4) and with carrier substrate (1, fig 4), the nodules (5, fig 4) having a thickness (thickness of 5) , along an axis (x-axis) normal to the main plane, less than or equal to 30 nm (between 20nm -5000), each nodule being disjunct or joined (dashed line) [0061], the disjunct nodules being separated (by cavities not illustrated which separate the metal material nodules) [0061 ] from one another by regions of direct contact between the working layer (3, fig 4) [0061]and the carrier substrate (1, fig 4) [0061]. Gondcharton do not teach the working layer made of monocrystalline semiconductor material. Katkar does teach the working layer made of monocrystalline semiconductor material. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Katkar into the structure of Gondcharton to include the working layer made of monocrystalline semiconductor material as claimed. The ordinary artisan would have been motivated to modify Gondcharton based on the teaching of Katkar in the above manner for the purpose of improving the reliable bonding [0005]. Re claim 3 Gondcharton in view of Katkar teach the semiconductor structure of claim 1, wherein the semiconductor material of the working layer (110b, fig 1B) [0021] is chosen from among silicon carbide, silicon, gallium nitride [Katkar, 0021]and germanium. Re claim 4 Gondcharton in view of Katkar teach the semiconductor structure of claim 1, wherein the semiconductor material of the carrier substrate (110a, fig 1B) [0021] is chosen from among silicon carbide, silicon, gallium nitride [Katkar , 0021] and germanium, and has a monocrystalline (single crystal), polycrystalline or amorphous structure. Re claim 5 Gondcharton in view of Katkar teach the semiconductor structure of claim 1, wherein the metal material of the nodules (5, fig 4) [0025] is chosen from among tungsten [Gondcharton, 0025], titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper. Re claim 6 Gondcharton in view of Katkar the semiconductor structure of claim 1, Gondcharton in view of Katkar not teach the degree of coverage of the nodules in a median plane of the interface zone is between 1% and 70%. Gondcharton does teach the degree of coverage of the nodules (5, fig 4) in a median plane of the interface zone is at least 50% (fig 4). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Gondcharton to include the degree of coverage of the nodules in a median plane of the interface zone is between 1% and 70%. as claimed. The ordinary artisan would have been motivated to modify Gondcharton in the above manner for the purpose of improving the quality of the bonding interface [0016]. “"[W]here the general conditions of claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller,220F.2d 454,456,105 USPQ 233,235(CCPA 1955)(MPEP Chapter 2100-Section 2144.05-optimization of ranges). Re claim 8 Gondcharton in view of Katkar teach the semiconductor structure of claim 1, wherein the nodules have a thickness of less than or equal to 20 nm. (between 20nm -5000nm) [0061]. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton modified by Katkar as applied to claim 1 and further in view of Bruel et al (US 8563399 B2). Re claim 2 Gondcharton in view of Katkar teach the semiconductor structure of claim 1, wherein the working layer (3, fig 4) [0061] and the carrier substrate (1, fig 4) [0061] are formed of the same semiconductor material (Silicon) [0061] and Gondcharton and Katkar do not teach the working layer and the carrier substrate have an identical doping type. Bruel teaches the working layer (2, fig 3B) [col 8, lines 40-45] and the carrier substrate (10, fig 3B) [col 8 lines 40-45] have an identical doping type [col 8, lines 40-45]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Bruel into the structure of Gondcharton and Katkar to include the working layer and the carrier substrate have an identical doping type as claimed. The ordinary artisan would have been motivated to modify Gondcharton and Katkar based on the teaching of Bruel in the above manner improve the functionality of the device. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton modified by Katkar as applied to claim 1 and further in view of Matocha et al (US 20150214164 A1). Re claim 7 Gondcharton in view of Katkar teach he semiconductor structure of claim 1, Gondcharton and Katkar do not teach the nodules have a resistivity lower than 0.1 mohm.cm2, so as to obtain a resistivity of the interface zone lower than 0.1 mohm.cm2. Matocha teaches the nodules have a resistivity lower than 0.1 mohm.cm2 (1.times.10.sup.-4 Ohm-cm.sup.2 i.e 0.1 mohm ⋅ cm² [0113] so as to obtain a resistivity of the interface zone lower than 0.1 mohm.cm2. [0113], It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught Matocha by into the structure of Gondcharton and Katkar to include the nodules have a resistivity lower than 0.1 mohm.cm2, so as to obtain a resistivity of the interface zone lower than 0.1 mohm.cm2 as claimed. The ordinary artisan would have been motivated to modify Gondcharton and Katkar in the above manner for the purpose of improving device stability [0012]. Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton modified by Katkar as applied to claim 1 and further in view of Nishiguchi et al (US20120025208A1). Re claim 9 Gondcharton in view of Katkar teach the semiconductor structure of claim 1, Gondcharton and Katkar do not teach the semiconductor structure comprises a power device including at least one component formed on and/or in the working layer, the semiconductor structure further comprising at least one electrical contact on and/or in the carrier substrate. Nishiguchi teaches, the semiconductor structure (101, fig 2, 8) comprises a power device [0084] including at least one component (127/110/127, fig 8) [0104] formed on and/or in the working layer (122, fig 8) [0104], the semiconductor structure (101, fig 8) further comprising at least one electrical contact ( 112, fig 8) on and/or in the carrier substrate (102, fig 8) [0104]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Nishiguchi into the structure of Gondcharton and Katkar to include the semiconductor structure comprises a power device including at least one component formed on and/or in the working layer, the semiconductor structure further comprising at least one electrical contact on and/or in the carrier substrate as claimed. The ordinary artisan would have been motivated to modify Gondcharton and Katkar based on the teaching of Nishiguchi in the above manner for the purpose of improving the efficiency of the device [0017]. Claims 10, 16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton in view of Katkar and Fournel et al (US 20050101095 A1). Re claim 10 and 20 Gondcharton teaches a method for producing a semiconductor structure, comprising: providing a working layer (3, fig 1) [0058] having a free face (bottom surface of 3, fig 1) to be joined; providing a carrier substrate (1, fig 1)[0058] made of semiconductor material (Silicon material) [0058] having a free face (top surface of 1, fig 1) [0058] to be joined; depositing a film (2/4, fig 2) [0058] made of a metal material (copper metal ) [0058] able to form an ohmic contact (contact between 3and 1) with the working layer (3, fig 1) [0058] and with the carrier substrate (1, fig 2) and having a thickness of less than or equal to 20 nm (20 nm -5000 nm) [0020] on the free face (bottom of 3) to be joined of the working layer (3, fig 2) and/or on the free face (top of 3) to be joined of the carrier substrate (1, fig 2) under a non-oxidizing controlled atmosphere (controlled atmosphere, vacuum)[0013]. forming an intermediate structure (5, fig 3-4) [0061] by directly joining the free faces to be joined of the working layer (3, fig 3-4) and of the carrier substrate (1, fig 3-4), respectively, under a non-oxidizing controlled atmosphere (controlled atmosphere, vacuum) [0013], the intermediate structure including an encapsulated film (4, fig 3-4) [0061] originating from the deposited film (2/4, fig 3-4)[0061] made of a metal material (copper, fig 3-4) [0061]; and annealing (annealing) [0062] the intermediate structure (5, fig 3-4) [0062] so as to cause segmentation of the encapsulated film (dashed line, 6 fig 3-4) [0061] into electrically conductive nodules (5, fig 3-4) forming an ohmic contact with the working layer (3, fig 3-4) and with the carrier substrate (1, fig 4), the nodules (5, fig 4) having a thickness, along an axis normal to a main plane of the working layer, less than or equal to 30 nm (20nm-5000nm) [0058], each nodule being disjunct or joined (dashed line 6, fig 4) [0061], the disjunct nodules being separated from one another by regions of direct contact between the working layer and the carrier substrate[0061]. Gondcharton does not teach the working layer made of monocrystalline semiconductor material. Katkar does teach the working layer made of monocrystalline semiconductor material. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Katkar into the structure of Gondcharton to include the working layer made of monocrystalline semiconductor material as claimed. The ordinary artisan would have been motivated to modify Gondcharton based on the teaching of Katkar in the above manner for the purpose of improving the reliable bonding [0005]. Gondcharton and Katkar do not teach annealing the intermediate structure at a temperature higher than or equal to a critical temperature-claim 10 and the critical temperature is between 500°C and 1800°C -claim 20. Fournel teaches “The wafer of silicon on which is bonded the film obtained by the separation undergoes a stabilization of the bonding by means of a thermal annealing at a temperature greater than around 600.degree. C” [0130]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Fournel into the structure of Gondcharton and Katkar to include annealing the intermediate structure at a temperature higher than or equal to a critical temperature claim 10 and the critical temperature is between 500°C and 1800°C. claim 20 as claimed. The ordinary artisan would have been motivated to modify Gondcharton and Katkar based on the teaching of Fournel in the above manner to improve the intermediate bonding. "[W]here the general conditions of claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller,220F.2d 454,456,105 USPQ 233,235(CCPA 1955)(MPEP Chapter 2100-Section 2144.05-optimization of ranges). Re claim 16 Gondcharton in view of Katkar and Frnck teach the method of claim 10, further comprising performing the depositing [0058-0061] of the film (2/4, fig 3-4) [0061] made of a metal material (copper) [0061] and the directly joining of the free faces (top of 1 and bottom of 3, fig 2-4) [0061] to be joined of the working layer (3, fig 2-4) [0061]and of the carrier substrate (1,fig 3-4) [0061] in one and the same apparatus (fig 4). Re claim 18 Gondcharton, Katkar and Fournel teach the method of claim 10, wherein the depositing of the film (2/4, fig 4) [0061] made of a metal material (copper, fig 4) [0061] and the directly joining of the free faces of the working layer (3, fig 4) and of the carrier substrate (1, fig 4) are performed in vacuum [0062]. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton modified by Katkar and Fournel as applied to claim 10 and further in view of Bruel et al (US 8563399 B2). Re claim 11 Gondcharton in view of Katkar and Frnck teach the method of claim 10, wherein the working layer (3, fig 4) [0058] and the carrier substrate (1, fig 4) [0058] are formed of the same semiconductor material (silicon) [0058-0061]. Gondcharton and Katkar do not teach the working layer and the carrier substrate have an identical doping type. Bruel teaches the working layer (2, fig 3B) [col 8, lines 40-45] and the carrier substrate (10, fig 3B) [col 8 lines 40-45] have an identical doping type [col 8, lines 40-45]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Bruel into the structure of Gondcharton, Katkar and Fournel to include the working layer and the carrier substrate have an identical doping type as claimed. The ordinary artisan would have been motivated to modify Gondcharton, Katkar and Fournel based on the teaching of Bruel in the above manner improve the functionality of the device. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton modified by Katkar and Fournel as applied to claim 10 and further in view of Bethoux et al (US 20110127581A1). Re claim 15 Gondcharton in view of Katkar and Fraanck teach the method of claim 10, Gondcharton and Katkar and Fournel do not teach prior to depositing the film made of a metal material, deoxidizing the free face to be joined of the working layer and/or of the free face to be joined of the carrier substrate. Bethoux teaches prior to depositing the film (bonding layer, 2, fig 4) [0196] made of a metal material, deoxidizing the free face to be joined of the working layer and/or of the free face to be joined of the carrier substrate. (the surfaces are cleaned to remove contaminants and deoxidizing treatment is performed on the surfaces) [0195]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Bethoux into the structure of Gondcharton and Katkar and Fournel to include prior to depositing the film made of a metal material, deoxidizing the free face to be joined of the working layer and/or of the free face to be joined of the carrier substrate as claimed. The ordinary artisan would have been motivated to modify Gondcharton and Katkar and Fournel based on the teaching of Bethoux in the above manner for the purpose of improving bonding efficiency. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton modified by Katkar and Fournel as applied to claim 10 and further in view of Okudo et al (US 20090159997 A1) Re claim 17 Gondcharton in view of Katkar and Fournel teach the method of claim 10, Gondcharton in view of Katkar and Fournel do not teach the deposited film made of a metal material has a thickness less than or equal to 10 nm. Okudo taches the deposited film made of a metal material (Au or Cu ) [0013] has a thickness less than or equal to 10 nm. (10nm) [0013]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Okudo into the structure of Gondcharton, Katkar and Fournel to include the deposited film made of a metal material has a thickness less than or equal to 10 nm as claimed. The ordinary artisan would have been motivated to modify Gondcharton, Katkar and Fournel based on the teaching of Okudo in the above manner for the purpose of achieving good bonding strength with an improved yield [0013]. "[W]here the general conditions of claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller,220F.2d 454,456,105 USPQ 233,235(CCPA 1955)(MPEP Chapter 2100-Section 2144.05-optimization of ranges). Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Gondcharton modified by Katkar and Fournel as applied to claim 10 and further in view of Tchkarov et al (US 20100225227 A1) Re claim 19 Gondcharton, Katkar and Fournel teach the method of claim 10, wherein the depositing of the film (2/4, fig 4) [0061] made of a metal material (copper) [0061] Gondcharton, Katkar and Fournel do not tech the deposition of the film performed at ambient temperature using a sputtering technique. Tchkarov tech the deposition of the film (the base layer, fig 2) [0107] performed at ambient temperature using a sputtering technique.[0107]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Tchkarov into the structure of Gondcharton, Katkar and Fournel to include the deposition of the film performed at ambient temperature using a sputtering technique as claimed because Sputtering is a known process in the art that is cost effective and better step coverage than conventional process. The ordinary artisan would have been motivated to modify Gondcharton, Katkar and Fournel based on the teaching of the Tchkarov in the above manner for the purpose of achieving desire thickness of the film. Allowable Subject Matter Claims 12-14 are objected to as being dependent upon a rejected base claim, but would be allowed if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818 /CALEB E HENRY/ Primary Examiner, Art Unit 2818
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Prosecution Timeline

Apr 30, 2024
Application Filed
Jul 22, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
97%
With Interview (+15.5%)
3y 2m (~11m remaining)
Median Time to Grant
Low
PTA Risk
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