Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-22 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by (Korean Patent No.: 10-2020-0042057) referring to Kim (Patent No.: US 11984434) for English version.
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Re claim 21, `434, FIG. 7B teaches a display device comprising:
a substrate (BS) including a pixel area including a first area [FA] and a second area [SA]; and
a pixel in each of the pixel area,
wherein the pixel comprises:
a pixel circuit part (SL/GIL/ISL/ETR/TCL/CDL/CPL) in the first area, the pixel circuit part comprising a bottom metal layer (ECNE) on the substrate, at least one transistor (ETR) on the bottom metal layer, and an interlayer insulating layer (left ISL) on the transistor; and
a display element part (PDA1/PAD2/CA1/CA2/ED/220) in the second area, the display element part comprising a plurality of light emitting elements to emit light (ED), an insulating pattern (right ISL) on the plurality of light emitting elements, and a bank (410) adjacent to the plurality of light emitting elements,
wherein the interlayer insulating layer (left ISL) and the insulating pattern (right ISL) comprise a same material, and
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wherein the bank (410, FIG. 4 [as shown above], note that 410 is occupied the outer portion of the display only) is entirely spaced from the plurality of light emitting elements (PDA1/PAD2/CA1/CA2/ED/220) and the pixel circuit part (SL/GIL/ISL/ETR/TCL/CDL/CPL) in a direction perpendicular to a thickness direction of the substrate (BS).
Re claim 22, `434, FIG. 7B teaches the display device of claim 21, wherein
each of the pixel circuit part (SL/GIL/ISL/ETR/TCL/CDL/CPL) and the display element part (PDA1/PAD2/CA1/CA2/ED/220) comprises a multilayer structure comprising at least one conductive layer and at least one insulating layer, and
at least one layer (ISL) of the pixel circuit part and at least one layer of the display element part are at a same layer and comprise a same material.
Claim(s) 21-22 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Kim (Patent No.: US 10373985).
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Re claim 21, Kim, FIG. 12 teaches a display device comprising:
a substrate (201) including a pixel area including a first area [LED] and a second area [PCP]; and
a pixel in each of the pixel area,
wherein the pixel comprises:
a pixel circuit part [PCP] in the first area, the pixel circuit part comprising a bottom metal layer (208 of FIG. 2, col. 6, lines 20-23) on the substrate, at least one transistor (203) on the bottom metal layer, and an interlayer insulating layer (right 212) on the transistor; and
a display element part [LED] in the second area, the display element part comprising a plurality of light emitting elements to emit light (233), an insulating pattern (left 212) on the plurality of light emitting elements, and a bank [aB] adjacent to the plurality of light emitting elements,
wherein the interlayer insulating layer and the insulating pattern comprise a same material (212), and
wherein the bank ([aB], FIG. 2 [as shown above]) is entirely spaced from the plurality of light emitting elements [LED] and the pixel circuit part [PCP] in a direction perpendicular [P] to a thickness direction of the substrate (201).
Re claim 22, Kim, FIG. 12 teaches the display device of claim 21, wherein
each of the pixel circuit part (1203/1210/1211/1208/1202/1207/1209) and the display element part (1213/1217/233/230/1214/1202/1207/1209) comprises a multilayer structure comprising at least one conductive layer and at least one insulating layer, and
at least one layer (1202) of the pixel circuit part and at least one layer of the display element part are at a same layer and comprise a same material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of `434.
Re claim 23, Kim, FIG. 12 teaches the display device of claim 22, wherein:
the insulating layer in the pixel circuit part comprises a buffer layer (1202), a gate insulating layer (1207), the interlayer insulating layer (1209), and a first insulating layer (right 1212) that are sequentially arranged on the substrate;
the insulating layer in the display element part comprises the buffer layer (1202) on the substrate, the insulating pattern (1209) on the buffer layer, and the first insulating layer (left 1212) on the insulating pattern;
Kim fails to teach the conductive layer in the pixel circuit part comprises the bottom metal layer between the substrate and the buffer layer, a first conductive layer between the gate insulating layer and the interlayer insulating layer, and a second conductive layer between the interlayer insulating layer and the first insulating layer; and
the conductive layer in the display element part comprises a first electrode and a second electrode that are between the substrate and the buffer layer and are spaced from each other, and a first contact electrode and a second contact electrode spaced from each other on the insulating pattern.
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`434, FIG. 7B teaches the conductive layer in the pixel circuit part comprises the bottom metal layer (ECNE) between the substrate (BS) and the buffer layer (GIL), a first conductive layer (EOE) between the gate insulating layer (ISL) and the interlayer insulating layer (TCL), and a second conductive layer (CDL) between the interlayer insulating layer (TCL) and the first insulating layer (CPL); and
the conductive layer in the display element part comprises a first electrode (PAD1, FIG. 8) and a second electrode (PAD2) that are between the substrate (BS) and the buffer layer (GIL) and are spaced from each other, and a first contact electrode (CA1) and a second contact electrode (CA2) spaced from each other on the insulating pattern (ISL).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of connecting to a power voltage as taught by `434, col. 2, lines 1-5.
Re claim 24, in the combination, `434, FIG. 8 teaches the display device of claim 23, wherein the plurality of light emitting elements (220) is on the buffer layer between the first electrode (PAD1) and the second electrode (PAD2).
Re claim 25, in the combination, `434, FIG. 8 teaches the display device of claim 23, wherein the bottom metal layer (ECNE) and the first (PAD1) and second electrodes (PAD2) are at a same layer, and comprise a same material.
Re claim 26, in the combination, Kim, FIG. 2 teaches the display device of claim 23, wherein: the second area comprises an emission area (233) from which the light is emitted; and the bank (212) does not overlap the emission area, is the bank being between the buffer layer (202) and the first insulating layer (217).
Re claim 27, in the combination, Kim, FIG. 2 teaches the display device of claim 26, wherein when viewed in a plan view, the bank (by looking down from top of 212) is around the plurality of light emitting elements (233).
Re claim 28, in the combination, `434, FIG. 8 teaches the display device of claim 26, wherein the buffer layer (GIL) of the display element part exposes a portion of each of the first (PAD1) and second electrodes (PAD2).
Re claim 29, in the combination, `434, FIG. 8 teaches the display device of claim 28, wherein:
the first contact electrode (CA1) is on the buffer layer and connected to the first electrode (PAD1) and each of the plurality of light emitting elements (220/PX of FIG. 4);
the second contact electrode (CA2) is on the buffer layer and connected to the second electrode (PAD2) and each of the plurality of light emitting elements; and
the first insulating layer (ISL) is on the first and second contact electrodes to cover the first and second contact electrodes.
Re claim 30, in the combination, `434, FIG. 8 teaches the display device of claim 29, wherein:
the substrate includes a display area (AA) in which the pixel area is located and a non-display area at least one side of the display area; and
the non-display area (NAA, FIG. 4) comprises the buffer layer, the gate insulating layer, the interlayer insulating layer, a wire part (of FIG. 6 connected to 220b) on the interlayer insulating layer, and a pad part connected to the wire part,
wherein the pad part comprises:
a first pad electrode (PAD1) on the interlayer insulating layer; and
a second pad electrode (CDL & DCL-3 of FIG. 10) on the first pad electrode and in contact with the first pad electrode.
Re claim 31, `434 differs from the invention by not showing wherein the second pad electrode comprises a same material as the first and second contact electrodes.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching b since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Re claim 32, in the combination, Kim, FIG. 2 teaches the display device of claim 31, further comprising a light blocking layer (217) on the first insulating layer (212) in each of the first and second areas.
Re claim 33, in the combination, Kim, FIG. 2 teaches the display device of claim 32, wherein the light blocking layer comprises a black matrix (217, col. 8, lines 24-26), and is not located in the emission area of the second area.
Re claim 34, in the combination, Kim, FIG. 4 teaches the display device of claim 32, further comprising:
a second insulating layer (419) on the first insulating layer (412) on the first and second contact electrodes and on the light blocking layer (418); and
a light converting pattern layer (416) in the emission area of the second area and on the second insulating layer.
Re claim 35, in the combination, Kim, FIG. 4 teaches the display device of claim 34, further comprising a planarization layer (419) on the light converting pattern layer (416).
Re claim 36, in the combination, Kim, FIG. 12 teaches the display device of claim 34, wherein:
the transistor comprises:
an active pattern (1206) on the buffer layer (1202) on the bottom metal layer (1206);
a gate electrode (1208) on the gate insulating layer (1207) on the active pattern and overlapping the active pattern; and
a first terminal (1210) and a second terminal (1211) contacting respective ends of the active pattern
wherein the first conductive layer comprises the gate electrode (1208).
Response to Arguments
Applicant's arguments filed 12/03/2025 have been fully considered but they are not persuasive. Please see the detail of the rejections as listed above.
For the above reasons, it is believed that the rejections should be sustained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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