DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on January 17, 2023 and July 31, 2025 have been considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Claims 6-8 (Invention II) in the reply filed on August 24, 2026 is acknowledged. Claims 1-5 and 9-10 are considered withdrawn.
Claim Objections
Claims 6-8 objected to under 37 CFR § 1.75 as depending from withdrawn claims 1 and 5. Rewrite claim 6 in independent form including all limitations of claims 1 and 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0279597 A1 to Jian-Ping Wang, et al. (hereafter Wang) in view of US 2019/0258482 A1 to Akhilesh Ramlaut Jaiswal, et al. (hereafter Jaiswal).
Regarding Claim 6, Wang discloses a method for calculating a Hamming distance based on the spin orbit torque magnetic random access memory array according to claim 5 (A spin orbit torque memory device wherein cells comprise a magnetic tunnel junction, a first transistor coupled to the bottom of the MTJ, a second transistor couple to the top of the MTJ, and relevant Read, Write, and Source lines: Wang, Figure 3 and ¶¶[0048-49]), comprising:
turning on the second transistor (Second transistor: Wang, Figure 3) and injecting an initialization current (Injecting an initialization current: Wang, ¶[0045]),
so that the magnetic tunnel junction produces a spin transfer torque effect (Setting the orientation of the magnetic moment: Wang, ¶[0045]) and
the magnetic tunnel junction is initialized to a high resistance state (Setting to a high resistance state: Wang, ¶[0044]);
performing an in-memory XOR operation on the first binary string information and the second binary string information (Performing an XOR comparison of data: Wang, ¶[0107]), and
storing in-memory XOR operation results in the spin orbit torque magnetic random access memory array (Storing the results of the operation back to an array cell: Wang, ¶[0053]); and
turning on the second transistor controlled by the bit read line,
reading the in-memory XOR operation results stored in the spin orbit torque magnetic random access memory array according to a voltage difference between the source line and the read bit line (Turning on the read resistor and reading the corresponding data: Wang, ¶[0051]), and
determining the Hamming distance (Performing a bitwise comparison to determine similarity: Wang, ¶[0110]).
Wang discloses performing an XOR using computational RAM, not encoding both strings as voltages on the write bit line and the source line of the result cell. Jaiswal, however, discloses a spin-torque memory cell array wherein:
encoding a first binary string information and a second binary string information in the write bit line and the source line, respectively, turning on the first transistor (Performing an XOR operation by driving a first binary operand to an array line, enabling the cell transistor, and writing the XOR into the cell: Jaiswal, ¶[0049]),
Jaiswal teaches this line-voltage operand encoding method saves energy on average (~50%) as both SL and BL lines are only charged if the bits differ (Jaiswal, ¶[0050]). A person having ordinary skill in the art, before the effective filing date of this application, would have been motivated to combine the efficient XOR line-voltage operand method of Jaiswal to Wang’s existing WBL-SL write path architecture, with a reasonable expectation of success. Using both ends of the SOT channel (WBL and SL) rather than a single line is a natural extension of Jaiswal’s three-terminal SOT cell. Both inventions are well known in the field of spin-torque memory cell operands and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 7, Wang discloses the method for calculating a Hamming distance according to claim 6, wherein
the in-memory XOR operation results are stored in the spin orbit torque magnetic random access memory cells located in a diagonal of the spin orbit torque magnetic random access memory array (The XOR operation results stored in data cells diagonally across the array: Wang, Figure 13).
Regarding Claim 8, Wang discloses the method for calculating a Hamming distance according to claim 6, wherein
the first binary string information and the second binary string information comprise N-bit characters, and N is a positive integer (The similarity output string matches the N number of source lines: Wang, Figure 13).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0210127 A1 to Marc Drouard: A SOT-MRAM cell comprising pairs of MTJ cells coupled to bit lines.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/PHO M LUU/Primary Examiner, Art Unit 2824
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