DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action (second Final Rejection) is in response to Amendment filed on January 12, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-4, 9-10, 14-18, 20 and 31-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the newly added limitation “the coherent interface between the first metallic layer and the channel layer, a bottom surface of the channel layer and a bottom surface of the gate stack are substantially coplanar: or the coherent interface between the second metallic layer and the channel layer, a top surface of the channel layer, and a top surface of the gate stack are substantially coplanar” recited on lines 13-17 is not incorporated by the original disclosure of current application, because Applicant did not originally disclose the recited coplanarity relationship among the coherent interface, the channel layer surface, and the gate stack surface, and Applicant did not originally disclose that the drawings of current application are exactly to the scale. In addition, when Applicant did not originally disclose coplanarity of the claimed interface and surfaces, Applicant did not originally disclose the claimed substantial coplanarity of the claimed interface and surfaces, because Applicant did not originally disclose how close to coplanarity it should be to be referred to be “substantially coplanar.” Furthermore, Applicant originally disclosed that the channel layer 1009 is disposed directly on a top surface of the first source/drain layer 1007 (Figs. 8c-9), and a bottom surface of the first source/drain layer 1007 is coplanar with a bottom surface of the gate stack (i.e., a bottom surface of the gate dielectric 1019, Fig 8c), and therefore, the bottom surface of the channel layer 1009 would not be coplanar with the bottom surface of the gate stack. Therefore, this claimed limitation fails to comply with the written description requirement. Claims 3-4, 9-10, 14-18, 20 and 31-32 depend on claim 1, and therefore, claims 3-4, 9-10, 14-18, 20 and 31-32 also fail to comply with the written description requirement.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over by Cheng et al. (US 2017/0338334, hereinafter Cheng) in view of Balakrishnan et al. (US 2019/0189745, hereinafter Balakrishnan).
Regarding claim 11, Cheng further discloses for a semiconductor device comprising that
a substrate (substrate 30, Fig. 7);
a first conductive layer (metal semiconductor alloy layer 10, Fig. 7), a first source/drain layer (source or drain region 70, [0040], Fig. 7), a channel layer (channel region 35, Fig. 7), a second source/drain layer (70, Fig. 7), and a second conductive layer (top contact 75, Fig. 7) which are sequentially disposed on the substrate (Fig. 7); and
a gate stack (gate structure 50/60, Fig. 7) formed around at least a part of a periphery of the channel layer (35, Fig. 7),
wherein each of the first conductive layer (10, Fig. 7), the second conductive layer (75, Fig. 7), the first source/drain layer (70, [0040]. Fig. 7), the second source/drain layer (70, Fig. 7), and the channel layer (35, Fig. 7) is of single crystal structure, because Cheng further discloses “Examples of suitable silicides for the metal semiconductor alloy 10 may include nickel monosilicide, cobalt silicide (CoSi2), a nickel silicide (NiSi2)…” ([0023]), therefore, the metal semiconductor alloy 10 is made of the same material composition of the claimed first conductive layer 1005 and in semiconductor industry, it is well-known that the NiSi2 or CoSi2 can form a single crystal structure, (2) Cheng further disclose “because the semiconductor surface layer 5a is composed of a monocrystalline material, the epitaxially formed channel region 35 may also be composed of a monocrystalline material” (emphasis added, [0047]), and (3) Cheng further disclose “the top contact 75 may be composed of copper, aluminum, tungsten, platinum or an alloy thereof” ([0054]) and in semiconductor industry, it is well-known that Cu, Al, W, Pt and its alloy can have a single crystal structure.
Cheng differs from the claimed invention by not showing that a difference between a lattice constant of each of the first conductive layer (10, Fig. 7) and the second conductive layer (75, Fig. 7) and a lattice constant of the substrate (30, Fig. 7) is within a range of +/- 2%.
However, Balakrishnan discloses for a MOSFET device having vertically oriented source/drain regions and channel region (Fig. 1) that the device includes a supporting substrate 5, a heavily doped source region layer 7/source doping 25, a channel region 20, and drain region 30 that are vertically oriented (Fig. 1), and therefore, the heavily doped source region layer 7 and drain region 30 correspond to the first and second conductive layers in the claimed invention, respectively; Balakrishnan further discloses that “the supporting substrate 5 is typically composed of a semiconductor material, such as a type IV semiconductor, e.g., silicon…” (emphasis added, [0037]), “the heavily doped source region layer 7 can be epitaxially formed semiconductor materials, which can be type IV semiconductors, such as silicon (Si), germanium (Ge), and/or silicon germanium (SiGe), or can be type IIIV semiconductors, such as gallium arsenide (GaAs)” (emphasis added, [0037]), and “the epitaxially formed drain region 30 may be composed of a type iV semiconductor, such as silicon, silicon germanium and/or germanium…” (emphasis added, [0047]), therefore, the substrate, the source region, and the drain region by Balakrishnan are made of silicon; since these layers can be formed of the same material (silicon), the difference between a lattice constant of the source region (the claimed first conductive layer) and drain region (the claimed second conductive layer) and the supporting silicon substrate (the claimed substrate) would be within a range of +/- 2%, as claimed. Examiner notes that Applicant does not specifically claim what the first and second conductive layers are made, what materials composition the first and second conductive layers have, and/or whether they are semiconductor material or metallic material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a lattice constant of the conductive layer and the substrate of a vertical channel MOSFET can be matched, as disclosed by Balakrishnan, in order to optimize the performance of a vertical MOSFET device.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over by Cheng et al. (US 2017/0338334, hereinafter “Cheng”) in view of Balakrishnan et al. (US 2019/0189745, hereinafter Balakrishnan) as applied to claim 11, and further in view of Ramaswamy (US 2019/0267495). The teachings of Cheng in view of Balakrishnan are discussed in claim 11 above.
Regarding claim 13, Cheng in view of Balakrishnan differs from the claimed invention by not showing that each of the first conductive layer and the second conductive layer comprises doped GaAs or doped GaAs:Si.
However, Ramaswamy discloses for a vertically-oriented transistor (Fig. 1) that the source/drain 18 comprises a region or portion 28 (Fig. 1, [0023]) and the portion 28 can correspond to the first conductive layer in the claimed invention; the source/drain 16 comprises a region or portion 26 (Fig. 1, [0023]) and the portion 26 can correspond to the second conductive layer in the claimed invention; Ramaswamy further discloses that “the at least one of the elemental silicon and the metal material od the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the respective source/drain region” (emphasis added. [0023]), therefore, one of ordinary skill in the art would acknowledge that a conductive layer directly contacted with source/drain can comprise GaAs.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that conductive layers directly contacted to source/drain region of a vertically-oriented transistor device can be made of doped GaAs, as disclosed by Ramaswamy, in order to optimize and improve the performance of the semiconductor device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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