Prosecution Insights
Last updated: October 22, 2026
Application No. 18/012,513

DISPLAY APPARATUS, DISPLAY MODULE, AND ELECTRONIC DEVICE

Final Rejection §103
Filed
Dec 22, 2022
Priority
Jul 03, 2020 — JP 2020-115385 +1 more
Examiner
JUNGE, BRYAN R.
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
4 (Final)
58%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
67%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
364 granted / 628 resolved
-10.0% vs TC avg
Moderate +9% lift
Without
With
+9.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
27 currently pending
Career history
665
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
63.3%
+23.3% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
17.4%
-22.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 628 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's amendments and the accompanying arguments filed 07/20/2026 have been fully considered but they are not persuasive. Applicant argued the references alone or in combination do not teach or render obvious a part of the conductive layer and a part of the first wiring are between the first pixel electrode and the second pixel electrode and the conductive layer surrounds the first pixel electrode in a plan view because Cha does not teach a conductive layer and Bang does not teach the conductive layer 109b/109c surrounds the first pixel electrode 109a when viewed in a plan view. However, Bang clearly teaches the conductive layer 109b, 109c surrounds the pixel electrode 109a, and additionally, that first wiring 106c is between the pixel electrodes 109a, see Figure 6, annotated below [AltContent: connector][AltContent: textbox (Example of conductive layer 109b, 109c surrounding pixel electrode 109a)][AltContent: arrow][AltContent: textbox (Example of first wiring 106c between pixel electrodes 109a)][AltContent: arrow]While no reference singly teaches the conductive layer or first wiring relative to the first pixel electrode (of the light-receiving element), one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, Cha teaches the light-receiving element comprising the first pixel electrode and the light emitting element comprising the second pixel electrode and Bang teaches the conductive layer between and surrounding all pixels and the first wiring between all pixels. The natural result of the combination of Cha and Bang, to apply the conductive layer 109b, 109c and the first wiring 106c of Bang to the display of Cha or to modify a pixel of Bang to be a light receiving pixel, results in a part of the conductive layer and a part of the first wiring being between the first pixel electrode and the second pixel electrode and the conductive layer surrounding the first pixel electrode in a plan view. Applicant highlighted features of Figure 5B in the remarks as an example of the claimed invention. However, distinguishing Figure 5B from that suggested by the prior art appears to rely on unclaimed features with regard to where, and where not, the conductive layer and first wiring are located. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The combination of references renders the invention as claimed obvious. The rejection is therefore maintained. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 12, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (US 2021/0158751) in view of Bang et al. (US 2010/0127264) and Kanaya (US 2020/0127224). In reference to claim 1, Cha et al. (US 2021/0158751), hereafter “Cha,” discloses a display apparatus comprising: a light-receiving element OPD in Figures 12 and 13; and a light-emitting element LD, paragraph 87; wherein the light-receiving element comprises a first pixel electrode E1, a common layer HTL over the first pixel electrode, an active layer OPL over the common layer, and a common electrode E2 over the active layer, paragraphs 189-192, wherein the light-emitting element comprises a second pixel electrode AE, the common layer HCL over the second pixel electrode, a light-emitting layer EML over the common layer, and the common electrode CE over the light-emitting layer, paragraphs 183-185 wherein the common layer is in contact with the first pixel electrode (HTL on E1) and the second pixel electrode (HCL on AE), paragraph 190, and wherein the common electrode comprises E2 overlapping with the first pixel electrode and a portion CE overlapping with the second pixel electrode, paragraph 192. Cha does not disclose a conductive layer, a first wiring, wherein the conductive layer is provided over the same surface as the first pixel electrode and the second pixel electrode, is positioned between the first pixel electrode and the second pixel electrode, is electrically connected to the common layer, and is electrically connected to the first wiring to which a first potential is supplied, wherein the common layer is in contact with the conductive layer, wherein the first wiring is provided over a surface different from the surface where the conductive layer is provided, wherein in a plan view, a part of the conductive layer and a part of the first wiring are between the first pixel electrode and the second pixel electrode, and wherein in a plan view, the conductive layer surrounds the first pixel electrode. Bang et al. (US 2010/0127264), hereafter “Bang,” discloses a display device including teaching a conductive layer 109b, 109c, and a first wiring, 106c in Figures 6 and 7, wherein the conductive layer is provided over the same surface (of 108) as a first pixel electrode 109a and a second pixel electrode 109a, is positioned between the first pixel electrode and the second pixel electrode, and is electrically connected to the first wiring 106c to which a first potential is supplied (common, cathode voltage), and wherein the first wiring is provided over a surface (of 105) different from the surface (of 108) where the conductive layer is provided, paragraphs 13, 39, and 41. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the display device to include a conductive layer and a first wiring, wherein the conductive layer is provided over the same surface as the first pixel electrode and the second pixel electrode, is positioned between the first pixel electrode and the second pixel electrode, and is electrically connected to the first wiring to which a first potential is supplied, wherein the first wiring is provided over a surface different from the surface where the conductive layer is provided, One would have been motivated to do so in order to couple the common electrode (cathode) to a pad area in a non-display region (106c to 26), Figure 2 and paragraph 37. In reference to a part of the conductive layer and a part of the first wiring are between the first pixel electrode and the second pixel electrode in a plan view, and the conductive layer surrounds the first pixel electrode in a plan view, Bang teaches the first wiring 106c between pixel electrodes 109a and the conductive layer 109b, 109c surrounds the pixel electrodes 109a of the light emitting elements, it results naturally from modifying the pixels of Cha to include the first wiring between pixels and the conductive layer surrounding the pixels as suggested by Bang that a part of the conductive layer and a part of the first wiring are between the first pixel electrode and the second pixel electrode in a plan view, and the conductive layer surrounds the first pixel electrode in a plan view. Bang does not disclose the conductive layer is electrically connected to the common layer, or wherein the common layer is in contact with the conductive layer. Kanaya (US 2020/0127224), hereafter “Kanaya,” discloses an analogous display device including teaching a conductive layer, 62 in Figure 2, wherein the conductive layer is provided over the same surface as the first pixel electrode 38 and the second pixel electrode 38, is positioned between the first pixel electrode 38 and the second pixel electrode 38, is electrically connected to the common layer 44, wherein the common layer 44 is in contact with the conductive layer, paragraph 42. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the display device to comprise a conductive layer, wherein the conductive layer is provided over the same surface as the first pixel electrode and the second pixel electrode, is positioned between the first pixel electrode and the second pixel electrode, is electrically connected to the common layer, wherein the common layer is in contact with the conductive layer. One would have been motivated to do so in order to ground a leakage current from the common layer, paragraph 46. In reference to claim 2, Cha discloses a first transistor and a second transistor, wherein the first pixel electrode is supplied with a second potential through the first transistor FT1, paragraph 136 and 175, and wherein the second pixel electrode is supplied with a third potential through the second transistor T1, paragraph 124. The second potential being lower than or equal to the first potential and the third potential being higher than or equal to the first potential are intended use limitations. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this case, the first and second transistors of Cha are capable of applying the respective lower or higher potentials. In reference to claim 3, Cha discloses the common electrode is supplied with the first potential, paragraph 193. In reference to claim 4, Cha discloses a first transistor and a second transistor, wherein the first pixel electrode is supplied with a fourth potential through the first transistor FT1, paragraph 136 and 175, and wherein the second pixel electrode is supplied with a fifth potential through the second transistor T1, paragraph 124. The fourth potential being higher than or equal to the first potential and the fifth potential being higher than or equal to the first potential, and fifth potential being higher than the fourth potential are intended use limitations. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this case, the first and second transistors of Cha are capable of applying the respective potentials. In reference to claim 12, Bang discloses a display region, 12 in Figure 1, and a non-display region 14, wherein the first pixel electrode and the second pixel electrode are provided in the display region, wherein the conductive layer is provided in the display region, and wherein the conductive layer is electrically connected to the first wiring in the display region, paragraphs 26, 28, and 30. In reference to claim 15, Cha discloses a display module comprising the display apparatus and a connector or an integrated circuit, paragraphs 87, 95, and 96. In reference to claim 16, Cha discloses an electronic device comprising the display module and at least one of an antenna, a battery, a house, a camera, a speaker, a microphone, and an operation button, paragraph 48. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (US 2021/0158751) in view of Bang et al. (US 2010/0127264) and Kanaya (US 2020/0127224) as applied to claim 1 above and further in view of Lee et al. (US 2011/0043464). In reference to claim 21, Cha does not disclose wherein in a plan view, the first wiring has a first region extending in a longitudinal direction of the light-receiving element, and wherein the first region does not overlap with the first pixel electrode and the second pixel electrode, and overlaps with a second region of the conductive layer extending in the longitudinal direction of the light receiving element. Bang discloses the conductive layer 109b, 109c, and a first wiring, 106c in Figures 6 and 7, wherein in a plan view, the first wiring has a first region 106c, and wherein the first region does not overlap with the first pixel electrode 109a and the second pixel electrode 109a, and overlaps with a second region of the conductive layer 109c, paragraphs 13, 39, and 41. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the display device to include a conductive layer and a first wiring, wherein in a plan view, the first wiring has a first region, and wherein the first region does not overlap with the first pixel electrode and the second pixel electrode, and overlaps with a second region of the conductive layer. One would have been motivated to do so in order to couple the common electrode (cathode) to a pad area in a non-display region (106c to 26), Figure 2 and paragraph 37. Lee et al. (US 2011/0043464), hereafter “Lee,” discloses an analogous display device including teaching a light-receiving element, S in Figure 2, extending in a longitudinal direction perpendicular to the longitudinal direction of the light emitting elements R, G, B, paragraph 39. Bang teaches the first region, 106c as addressed above, extending in a longitudinal direction perpendicular to the longitudinal direction of the light emitting elements, Figure 6. It results naturally from the combination of Lee with Cha in view of Bang that the first region extends in a longitudinal direction of the light-receiving element, and the second region of the conductive layer extends in the longitudinal direction of the light receiving element. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first wiring to have a first region extending in a longitudinal direction of the light-receiving element in a plan view, and the first region to not overlap with the first pixel electrode and the second pixel electrode, and to overlap with a second region of the conductive layer extending in the longitudinal direction of the light receiving element. To do so would have merely been to apply a known technique to improve similar devices in the same way, KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. C. In this case, applying the first wiring and conductive layer of Cha in view of Bang to the pixel layout of Lee. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Akiyama (US 2013/0075761), Lee et al. (US 2020/0212138), Zhu et al. (US 10,984,208), Tanaka (US 2023/0243703), and KR 10-2020-0046817 A, disclose related display devices including light receiving pixels. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRYAN R JUNGE/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Show 1 earlier event
May 07, 2025
Non-Final Rejection mailed — §103
Aug 07, 2025
Response Filed
Oct 01, 2025
Final Rejection mailed — §103
Feb 02, 2026
Request for Continued Examination
Feb 10, 2026
Response after Non-Final Action
Apr 20, 2026
Non-Final Rejection mailed — §103
Jul 20, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
58%
Grant Probability
67%
With Interview (+9.0%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 628 resolved cases by this examiner. Grant probability derived from career allowance rate.

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