Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/18/2026 has been entered.
Response to Arguments
Applicant's arguments directed to the newly amended claims filed 3/9/2026 have been fully considered but they are not persuasive.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant's arguments directed to the newly amended claims filed 5/18/2026 have been fully considered but they are not persuasive.
The amendment adding "only by the conductive feature" fails to overcome the prior art because it relies on a mere semantic distinction that does not alter the physical structure. Even if the electrical path is restricted to the conductive feature, the physical layout remains identical to Lin’s structure where the corresponding layers are in direct physical and electrical contact at the interface. Because the physical arrangement is unchanged, this limitation is fully disclosed by the reference.
The contention that Lin fails to teach a rewiring layer with hollows is a conclusory denial that completely ignores the Examiner’s explicit mapping. Lin clearly discloses patterned, recessed structural configurations in Figures 3g-i that form the exact structural equivalent of the claimed hollows to manage contact area and stress. Without demonstrating a structural difference between the claimed hollows and Lin's illustrated recesses, the applicant's argument fails to establish patentable distinction.
The limitation requiring a pillar thickness greater than 30 microns is unpatentable because the claimed range directly overlaps with the prior art, rendering thickness a result-effective variable. Lin explicitly discloses a pin layer thickness of about 37 microns, and Zhai teaches a range of 30 to 50 microns. Because the claimed thickness is encompassed by these references, the applicant bears the burden of demonstrating criticality or unexpected results through routine experimentation, which they have failed to do.
The assertion that the claimed combination yields unexpected benefits in preventing delamination and enhancing signal stability is entirely unsupported by evidence. In patent prosecution, attorney argument cannot substitute for objective evidence or data. Because the applicant failed to provide comparative testing or an affidavit under 37 CFR 1.132 to substantiate these purported advantages, the prima facie case of obviousness stands unrebutted.
Mapping of Applicant’s Claim to representative figure 14 for clarity.
For clarity of interpretation the Applicant’s claim 1 is mapped to the Applicant’s figure 14 below.
Claim 1: A semiconductor packaging method, comprising: forming an encapsulating structure, the encapsulating structure comprising an encapsulation layer and a chip 20, the chip provided on a front side thereof with a plurality of bonding pads 21, the encapsulation layer 30 covering at least a side face of the chip 20;
forming a rewiring layer 41 on a side of the encapsulating structure close to the front side of the chip, the rewiring layer configured for external connection of the bonding pads on the chip 20;
forming a dielectric layer 50, the dielectric layer 50 covering the rewiring layer 41, the dielectric layer 50 provided therein with a through hole 24 in which the rewiring layer is exposed;
forming a pin layer 52/61 on a side of the dielectric layer 50 away from the chip 20, the pin layer 52/61 electrically connected to the rewiring layer 41 through the through hole 24, wherein the pin layer 52/61 comprises a plurality of conductive pillars 61 which are spaced apart from one another and raised from the dielectric layer 50 (Note: As best understood Fig. 14 only depicts a single pillar, however a plurality would be spaced as shown for example in fig. 12.), wherein the pin layer is spaced apart from the rewiring layer by the dielectric layer, and
forming a solder layer 70, the solder layer 70 covering both side surfaces and a top surface of the plurality of conductive pillars 52/61 away from the chip, wherein the rewiring layer 41 comprises a plurality of rewiring structures (i.e. Fig. 12 for plurality arrangement) which are spaced apart from one another and provided with hollows (i.e. corresponding to holes 51) to reduce a contact area of the rewiring layer 41 with the dielectric layer 50 and prevent separation of the rewiring structures 41 from the dielectric layer 50,
wherein the plurality of conductive pillars 52/61 have a thickness greater than 30 micrometers wherein a conductive feature 52/61 is provided in the through hole 51 so that the pin layer is electrically connected to the rewiring layer only by the conductive feature filled in the through hole, wherein a recess is formed in the conductive feature 52/61 in positional correspondence with the through hole 51, and the solder layer 70 fills the recess.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-14, 16-19, 21 and 1, 3,-5, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20160276237 A1) in view of Zhai et al. (US 20160260684 A1)
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CLAIMS 9 & 1. Lin et al. discloses a semiconductor packaging structure, comprising:
an encapsulating structure 156 , the encapsulating structure comprising an encapsulation layer 156 and a chip 124,
the chip 124 provided on a front side thereof with a plurality of bonding pads 132, the encapsulation layer covering a backside and a side face of the chip (Lin Fig. 7);
a rewiring layer 170 located on a side of the encapsulating structure close to the front side of the chip 124, the rewiring layer configured for external connection of the bonding pads on the chip (Lin Fig. 18);
a dielectric layer 160/172 covering the rewiring layer, the dielectric layer provided therein with a through hole 174 in which the rewiring layer 172 is exposed (Lin Fig. 18); and
a pin layer 176 located on a side of the dielectric layer 172 away from the chip, the pin layer 402 electrically connected to the rewiring layer 170 through the through hole 174, wherein the pin layer 402 comprises a plurality of conductive pillars 402 which are spaced apart from one another and raised from the dielectric layer 172 (Lin Fig. 18); and
a solder layer 408 covering both side surfaces and a top surface of the plurality of conductive pillars away from the chip (Lin Fig. 18);
wherein the rewiring layer 170 comprises a plurality of rewiring structures which are spaced apart from one another and provided with hollows [Figs. g-i) to reduce a contact area of the rewiring layer with the dielectric layer and prevent separation of the rewiring structures from the dielectric layer (Lin Fig. 3g-I depict analogous “hollows”.).
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wherein a conductive feature 402 is provided in the through hole so that the pin layer 402 is electrically connected to the rewiring layer 170 only by the conductive feature 402 filled in the through hole, wherein a recess 176 is formed in the conductive feature 402 in positional correspondence with the through hole, and the solder layer 408 fills the recess (Lin Fig. 18).
Regarding wherein the pillar has a thickness greater than 30 μm. As understood from the Applicant’s written description and figures, pillar is the total thickness of pin layer which is analogous to layer 402 of Lin..
Lin et al. is silent upon the specific thickness of the of the pin layer cited in figures 3-7, however as disclosed within various embodiments such as shown in figure 15a, the pin layer of the embodiment has a total thickness of about 37 μm. Thus it would be a obvious expectation, the analogous pin layer as identified in figures 3-7 would be capable of having a pin layer having a similar thickness.
Should the interpretation be intended to be limited to the portion of the pin layer over the dielectric layer, this thickness was a known capability in the art at the time of the invention. For a generic example of RDL layers, including pad/pillar portions beign explicitly in the claimed range see Zhai et al.. Paragraph 41, teaches analogous “pin layers” similar to an RDL/UBM pad for providing a solder connection, may range from 30 μm to 50 μm.
As such, it would have been obvious for one of ordinary skill in the art (POSITA) to modify the Lin device to incorporate known device thicknesses disclosed in further embodiments of Lin or with parameters such as acknowledged in the Zhai reference. One skilled in the art of making semiconductor devices would have been motivated to determine the optimal or workable value for the thickness through routine experimentation and optimization. This is because thickness is a result-effective variable, there is no evidence indicating it is critical or produces unexpected results, and discovering optimal ranges of such variables within known prior art conditions through routine experimentation is generally considered uninventive (see MPEP § 2144.05)
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 11 & 3. Lin et al. discloses a semiconductor packaging structure according to claim 9, wherein a conductive feature is provided in the through hole so that the pin layer is electrically connected to the rewiring layer by the conductive feature, wherein a recess is formed in the conductive feature in positional correspondence with the through hole, , the solder layer filling the recess (Lin Figs 3 & 7).
CLAIM 12 & 4. Lin et al. discloses a semiconductor packaging structure according to claim 11, however may be silent upon wherein a width-to-depth ratio of the through hole is greater than or equal to 1/3.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ratio through routine experimentation and optimization to obtain optimal or desired device performance because the ratio is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 13 & 5. Lin et al. discloses a semiconductor packaging structure according to claim 12, however may be silent upon wherein a depth of the through hole ranges from 60 pm to 100 pm, and a thickness of the conductive feature at a bottom of the through hole ranges from 10 to 50 micrometer.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the dimensions through routine experimentation and optimization to obtain optimal or desired device performance because the dimensions is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 16. Lin et al. discloses a semiconductor packaging structure according to claim 15, further comprising: a protective layer formed on the front side of the chip, wherein the protective layer comprises openings in which the plurality of bonding pads are exposed; and conductive structures formed in the openings in the protective layer, wherein the rewiring structures are electrically connected to the bonding pads by the conductive structures (Lin Fig. 7).
CLAIM 17 & 7. Lin et al. discloses a semiconductor packaging structure according to claim 16, further comprising: a heat dissipation layer 402 located on the side of the dielectric layer away from the chip, wherein the plurality of conductive pillars are located around the heat dissipation layer (Lin Fig. 18 – The function al language of a “heat dissipation layer” does not provide a clear and explicit structural distinction. Applicant’s fig. 14 as best understood shows the pin layer having a portion meting the scope of a “pillar” in the central location, and the further extending regions would meet the scope describing a “heat dissipation” structure formed at the same time.).
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CLAIM 18 Lin et al. discloses a semiconductor packaging method according to claim 7, wherein the heat dissipation layer 402 is formed in the same process step in which the pin layer is formed (Lin Fig. 18 - The Pin layer and heat dissipation layer are the same layer, thus formed in the same process step.).
Further regarding CLAIM 1, 3, 4-5 & 7, see regarding claims 9, 11-13, 16-18 identifying analogous structural elements that are implicitly “formed” as recited in corresponding claims 1, 3, 4-5 & 7. The additional step of “forming” is considered an obvious procedural step when the prior art discloses the structural elements, and thus lacks inventive concept.
(Lin Fig. 18 – The function al language of a “heat dissipation layer” does not provide a clear and explicit structural distinction. Applicant’s fig. 14 as best understood shows the pin layer having a portion meting the scope of a “pillar” in the central location, and the further extending regions would meet the scope describing a “heat dissipation” structure formed at the same time.).
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CLAIM 19 Lin et al. discloses a semiconductor packaging method according to claim 1, wherein the dielectric layer comprises an inorganic dielectric material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride (Lin ¶65).
CLAIM 21 Lin et al. discloses a semiconductor packaging method according to claim 1, wherein the solder layer is in direct contact with the dielectric layer at a peripheral edge of the through hole (Lin Fig 18 – The solder layer of Lin is shown to be in contact with the dielectric layer in the same manner as shown by the Applicant’s fig. 14 representing the claimed subject matter.).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20160276237 A1) in view of Zhai et al. (US 20160260684 A1) in view of Lai et al. ( US 20160358889 A1).
CLAIM 20 Lin et al. discloses a semiconductor packaging method according to claim 1, however is silent upon wherein a depth of the through hole is greater than 60 pm, and a width-to-depth ratio of the through hole is less than 1/2.
While Lin may be silent regarding the specific through-hole dimensions of Claim 1, Lin discloses that through-hole thickness and size are optimizable parameters (see Table 1). The specific dimensions recited represent known, capable sizes for such features in the art.
Lai confirms this by teaching that through-dielectric contacts are routinely formed at depths well over 60 μm. Specifically, Lai discloses vertical routing paths exceeding 100 μm from package bottom surface contacts to second-level dies (Para. [0024]). Because Lin identifies these dimensions as variable parameters and Lai demonstrates that the claimed depths are standard in the industry, it would have been a routine design choice for one of ordinary skill in the art to implement Lin’s method within the specified size ranges to achieve desired package thickness and routing efficiency.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the dimensions through routine experimentation and optimization to obtain optimal or desired device performance because the dimensions is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
5/21/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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