Prosecution Insights
Last updated: October 04, 2026
Application No. 18/016,811

METHOD AND APPARATUS FOR IDENTIFYING CONTAMINATION IN A SEMICONDUCTOR FAB

Non-Final OA §101§102§103
Filed
Jan 18, 2023
Priority
Aug 11, 2020 — provisional 63/064,014 +3 more
Examiner
GASSEN, CHRISTOPHER J
Art Unit
2881
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
ASML Holding N.V.
OA Round
3 (Non-Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
109 granted / 137 resolved
+11.6% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
38 currently pending
Career history
169
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
16.4%
-23.6% vs TC avg
§112
31.1%
-8.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 137 resolved cases

Office Action

§101 §102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/15/2026 has been entered. Response to Amendment The amendments filed 07/15/2026 with the above entered RCE have accordingly been entered. Claims 19 has been canceled. New claim 23 has been added by way of amendment. Claims 1-9, 11-14, 16-18, and 20-23 are now pending in the application. Response to Arguments Applicant’s amendments to the claims have overcome each and every 35 U.S.C. 112(b) rejection previously set forth in the Final Office Action dated 01/15/2026, hereinafter FOA0115. Applicant’s arguments with respect to claims 1 and 14 have been considered but are moot because they pertain to amended claim limitations not present at the time of FOA0115. See below for a detail discussion of amended claim limitations. Nevertheless, for clarity of the record, in regards to Applicant’s argument that “…it is not apparent in what manner paragraph [0068] of Van Rhee describes a new data set, namely the combined contamination map data being a data set different than the respective contamination map data of each of the plurality of substrates, and which new set (which results from the combination of contamination map data from a plurality of substrates) being compared to reference data.”, Examiner first notes that this paragraph was not applied to such ‘different data set’ limitations, as such limitations were not previously present. Under the broadest reasonable interpretation (BRI), the limitation “…the combined contamination map data being a data set different than the respective contamination map data of each of the plurality of substrates; and comparing the combined contamination map data to reference data…”, requires that: (1) the combined contamination map data is a data set, (2) the data set be different than the respective contamination map data of each of the plurality of substrates, and (3) the combined contamination map data is compared to reference data. Limitation (1) does not particularly limit how the combined contamination map data is combined nor what it contains. The claim previously requires that the combined contamination map data be based at least in part on a combination of the contamination map data of the plurality of substrates. This limitation is clearly met by the cited portions of Van Rhee in FOA0115. Limitation (2) is understood as requiring that the combined contamination map data not be a duplicate of any of the respective contamination map data of each of the plurality of substrates. However, this limitation does not limit the combined contamination map data from including a combination of a plurality of such respective contamination map data for a plurality of such substrates as the combined contamination map data, as such a data set would be different from the respective contamination map data of each of the plurality of substrates. Accordingly, this limitation appears to be met by the cited portions of Van Rhee in FOA0115 as well. For completeness, Examiner refers back to the Response to Arguments section of FOA0115, p. 3-4, wherein the BRI of the disclosure of Van Rhee is discussed: “Examiner first notes that the actual process/manner of combining the contamination map data of the plurality of substrates is not limited in the claim. Accordingly, any ‘combination’ of such data reads on the limitation, such as merely storing such data in a common location or including the data in a common repository to be called up for comparison. Paragraph [0068] discusses comparing maps of successive substrates (i.e., samples) to determine correlations of faults between the samples to indicate a source of contamination in the system, which would inherently require retaining the data for each of the maps such that each new map can be compared thereto. While Van Rhee does not explicitly discuss ‘combining’ each of the contamination maps into ‘combined contamination map data’, Van Rhee clearly teaches to compare the maps for each of the substrates to the previously measured maps (i.e., a set of historical data comprising the previous maps), and in particular to include comparing to maps other than the immediately preceding map (i.e., the threshold level is not particularly limited). In other words, in Van Rhee, a collection of historical data (i.e., a collection of maps) is maintained and added to in order to compare each successive measured map to, thus allowing one to count the focus spots on a same position to determine if the number of focus spots exceeds a threshold. It is Examiner’s opinion that an ordinarily skilled artisan would understand a set of previously measured maps, which are to be each compared to a particular map, as reading on combined contamination data, as it represents the same information, regardless of the particular phrasing used by Van Rhee. This data would also inherently be different from any particular map data for any particular substrate. Under the BRI comparing a series of successive maps and retaining relative information between each of the maps could also be interpreted as combining the map data (but obviously would not read on combining the maps themselves, which is not required by the claim, but would be different from the respective maps of respective samples). For completeness, Examiner notes that the claim does not require that each of the measured maps be combined into a single combined contamination map including all of the information contained in previously measured maps, and merely requires ‘determining combined contamination map data’, but does not limit how the data is ‘combined’, which is broad enough to include various means and degrees of ‘combination’, nor how much/what portion(s) of the data need be combined. Examiner also notes that an ordinarily skilled artisan could also readily combine any number of historical data sets of the same kind (e.g., contamination maps) to form a single composite data set using solely their ordinary skill and conventional techniques.” Accordingly, under the BRI, it remains Examiner’s opinion that the cited portions of Van Rhee read on the requirements of this portion of the claim, including limitation (2). Limitation (3) is disclosed for similar reasons to those previously discussed in FOA0115 (see p. 5-6), the reasoning of which has not particularly been refuted by Applicant, and which is not changed in view of limitation (2). Examiner notes in particular, that the comparing is not particularly limited to any particular portions of the combined contamination map data and/or the reference data, and that the claim requires that the reference data include one or more values for the combined contamination map data that are indicative of contamination. In Van Rhee the historical data set includes data that is indicative of contamination in each previous data set (e.g., focus spots are indicative of contamination), the reference data of Van Rhee includes the historical set of data indicating focus spots, and Van Rhee discloses comparing different portions of the historical data set in sub-sets according to the thresholds desired. See below for further discussion of amended claim limitations. Applicant's arguments regarding claim 16 have been fully considered but they are not persuasive. Applicant argues that the cited portions of Van Rhee do not disclose ‘linking the identification of the one or more contamination spots with a step identified from among a plurality of steps in the processing of the semiconductor fab”. Applicant cites [0008] and [0068] and argues against the paragraphs. Examiner notes, in response to Applicant’s arguments regarding [0008], that [0008] was applied to indicate Van Rhee’s understanding of the scope/context of use (e.g., manufacturing ICs) and the varying terminology used in differing applications/contexts. Regarding [0068], Applicant argues “As for cited paragraph [0068] of Van Rhee, it similarly provides no disclosure regarding linking the identification of one or more contamination spots with a step identified from among a plurality of steps in the processing of the semiconductor fab, as claimed. Rather, it merely describes, for example, that detection of "...correlations in the locations of any unflatnesses [] may be indicative of contamination or systematic faults of said second object table." Thus, there is no apparent disclosure in the cited portions of Van Rhee of linking of contamination with a step identified from among a plurality of steps in the processing of the semiconductor fab. If "contamination or systematic faults of said second object table" is arguendo "a step in the processing of the semiconductor fab," then it is apparent that is not identified from among a plurality of steps; it would at best be just a single known step associated with the contamination. The cited portions of Van Rhee do not appear to disclose any technique to identify which step of among many steps in processing is linked to contamination.” Examiner respectfully disagrees. The limitation at issue requires “linking the identification of the one or more contamination spots with a step identified from among a plurality of steps in the processing of the semiconductor fab”. Under the BRI, this limitation requires: linking the identification of the one or more contamination spots with a step the step be identified from among a plurality of steps the plurality of steps are in the processing of the semiconductor fab. The limitation makes no requirements toward what the steps must be outside of being ‘in the processing of the semiconductor fab’. The limitation makes no requirement as to how the step must be linked, nor as to whether the step to be linked is known beforehand or unknown. Van Rhee discloses in [0068]: “In a method according to an embodiment of the invention, the subtracted height maps of successively provided substrates are compared. Such comparison may be used to detect correlations in the locations of any unflatnesses that may be indicative of contamination or systematic faults of said second object table. In this way, so-called `chuck spots` are located, and it may be decided to clean the substrate holder.”, which clearly indicates that the comparison may be used to detect correlations in the locations of any unflatnesses that may be indicative of contamination or systemic faults of said second object table. While Van Rhee does not explicitly recite (A), it discloses equivalent teachings. Van Rhee uses the location data of focus spots to identify contamination/systemic faults, and uses that data to determine when an element of the system needs to be cleaned. Identifying that the second substrate holder must be cleaned because it is causing contamination/systemic faults in samples is equivalent to linking identified contamination to a step in the semiconductor fab processing. In the semiconductor processing of Van Rhee, for the second sample holder to cause contamination/systemic faults of the samples, an ordinarily skilled artisan would readily understand that a processing step including the second sample holder communicating such contamination/systemic faults to the samples must have been performed (e.g., mounting, transferring, etc.; See, e.g., Background of Van Rhee). Similarly, while not explicitly recited, Van Rhee teaches equivalent disclosure to (B) and (C). An ordinarily skilled artisan would know that in the context of Van Rhee (i.e., post-processing evaluation of semiconductor samples), several processing steps would have typically been performed prior to such evaluation (see Van Rhee Background: [0003]-[0012]). Van Rhee specifically discloses that the second object table interacts with samples (and thus communicates any contamination/systemic faults) after first being processed on a first object table. The ‘step’ linked is the communication of the samples with the contaminated second object table/sample holder after the previous object table processing, hence the need for a subsequent cleaning step. While not explicitly stated in [0068], to reach the second object table, a sample would have already gone through processing on the first object table. Van Rhee links the contamination to the second object table, and thus, implicitly to the processing step associated therewith, which is one of a plurality of such steps, even if not explicitly referred to as ‘a step of a plurality of steps in processing’. An ordinarily skilled artisan would be readily apprised of how a sample holder would transfer contaminants to a sample (e.g. via mounting, transfer, etc.), would readily recognize Van Rhee as disclosing a plurality of steps in the processing of a semiconductor fab, and could readily recognize Van Rhee as teaching ‘linking…a step identified from among a plurality of steps in the processing of the semiconductor fab’ in context. Accordingly, Applicant’s argument that Van Rhee discloses no such linking is not convincing for the above reasons. in other words, whether Van Rhee explicitly refers to linking to a step does not change whether Van Rhee discloses such a limitation. Similarly, Applicant’s argument that a plurality of steps are not disclosed is not convincing, as the disclosure of Van Rhee clearly discloses various processing steps. Examiner notes that an ordinarily skilled artisan, reading Van Rhee, would readily identify numerous processing steps disclosed (see, e.g., background) under the BRI, even if not explicitly recited as ‘processing steps in a semiconductor fab’. Van Rhee discloses various functions in its background that would be understood by an ordinarily skilled artisan, under the BRI, ‘processing steps’. In other words, whether Van Rhee explicitly refers to the steps as processing steps does not change whether Van Rhee discloses such steps. Regarding Applicant’s argument that “The cited portions of Van Rhee do not appear to disclose any technique to identify which step of among many steps in processing is linked to contamination”, Examiner notes that this limitation is not required by the BRI of the claim. The claim does not require identifying a plurality of potential contamination steps, and determining which is the cause of contamination. The claim requires only identifying the contamination, and linking such contamination with a step among a plurality of steps. The other steps are not particularly limited and need not be potentially contamination causing, nor do they need to be considered for potential contamination, under the BRI, as presently claimed. As such, this argument is not convincing. Accordingly, Applicant’s arguments regarding claim 16 are not convincing. Applicant’s arguments regarding claims 13 and 18 are not convincing for similar reasons to those discussed above. Claim Objections Claims 14, 16, and 23 are objected to because of the following informalities: Claim 14 recites “…to control an apparatus to at least:…comparing the combined contamination map data to…”, which does not match grammatically, and should read ‘…to control an apparatus to at least:…compare the combined contamination map data to…’; Claim 16 recites “linking the identification of the one or more contamination spots with…”, however, if no such contamination spots exist, ‘the identification’ would not make sense; However, Examiner believes the limitation is definite in context and should merely be amended to ‘linking an identification of the one or more contamination spots with…’, such that the claim maintains consistency in the case of no identified contamination spots; Claim 23 suffers from a similar issue as claim 16, and should be similarly amended. Appropriate correction is required. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-9, 11-14, 16-18, and 20-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea judicial exception without significantly more. Claim 1 recites ‘a method for identifying contamination in a semiconductor fab, the method comprising: determining contamination map data…; determining combined contamination map data based, at least in part, on a combination of the contamination map data…; comparing the combined contamination map data to reference data…’. Claim 14 recites ‘a computer program product comprising a non-transitory computer-readable medium having instruction therein, the instructions, when executed on at least one processor, cause the at least one processor to control an apparatus to at least: determine contamination map data…, determine combined contamination map data based, at least in part, on a combination of the contamination map data…, comparing the combined contamination map data to reference data…’. Claim 16 recites ‘a method for identifying contamination in a semiconductor fab, the method comprising: determining contamination map data…; comparing the determined contamination map data with a previously obtained contamination map…to identify one or more contamination spots…; and linking the identification of the one or more contamination spots with a step identified from among a plurality of steps…’. Claim 23 recites a computer program product comprising a non-transitory computer-readable medium having instruction therein, the instructions, when executed on at least one processor, cause the at least one processor to control an apparatus to at least: determine contamination map data…; compare the determined contamination map data with a previously obtained contamination map…to identify one or more contamination spots…; and link the identification of the one or more contamination spots with a step identified from among a plurality of steps…’. The following analysis follows the MPEP subject matter eligibility test (See MPEP 2106, 2106.III). In step 1 (See MPEP 2106.03), claims 1-9, 11-14, 16-18, and 20-23 are directed to methods, with claims 14 and 23 pertaining to methods via a computer program. In step 2A (See MPEP 2106.04), a two pronged inquiry is required (MPEP 2106.04.II.A.1-2). In step 2A, prong one, claims 1-9, 11-14, 16-18, and 20-23 recite abstract idea judicial exceptions. In particular, claim 1 recites method steps requiring (i) determining data, (ii) determining data based at least in part on the previously determined data, (iii) comparing the data to reference data. This amounts to mere data manipulation and evaluation, as the method only requires determining data (i.e., reading data), forming an additional data set in part based on the determined data, and comparing the additional data set to reference data. No function is performed as a result of the comparison, nor is the data used to perform any action in the method. No particular method of determining the map data, determining the combined map data, or comparing the combined map to the reference data is required, and as such, this task can be performed in the human mind (i.e., by a human with a computer, see MPEP 2106.04(a)(2).III), as a human mind could reasonably determine combined data, based at least in part on the previous map data, with a generic computer screen, by identifying contamination in the maps and selecting the contamination portions, and could readily compare such a data set (e.g., on a screen of a generic computer) to reference (e.g., historical) data (e.g., on a screen of a generic computer). Accordingly, the claim recites at least a mental processing grouping judicial exception, as well as reciting mathematical concepts (See MPEP 2106.04(a)(2).I) as the method amounts to merely reading in data and performing calculations on the input data (e.g., partial additions, comparisons, unions, etc.). The presence of contamination in such map data is a mathematical fact, and generally determining (according to some threshold, as would be known by an ordinarily skilled artisan) such data can be performed by generic mathematical calculations. Similarly, combining data sets from existing data sets and comparing data sets to one another can be performed by generic mathematical calculations (e.g., adding, subtracting, determining unions, determining various statistics of the sets, etc.). Claim 14 recites similar limitations for a computer program product. Claim 16 recites method steps requiring (i) determining data, (ii) comparing the determined data to a previously obtained data to identify one or more contamination spots (i.e. data features) that have appeared or disappeared since the previously obtained data (i.e., comparing data), (iii) linking the identification of the one or more contamination spots to a step identified from among a plurality of steps in the processing of the semiconductor fab. This amounts to mere data manipulation and evaluation, as the method only requires determining data (i.e., reading data), comparing the determined data to previously obtained data to determine features in common/not in common, and linking such features to an identified processing step among a plurality of arbitrary processing steps. No function is performed as a result of the linking, nor is the linking used to perform any action in the method. No particular method of determining the map data, comparing the data to determine the contamination spots, or linking to a processing step is required, and as such, this task can be performed in the human mind (i.e., by a human with a computer, see MPEP 2106.04(a)(2).III), as a human mind could reasonably determine the map data, with a generic computer screen, by identifying contamination in the maps displayed thereon, and could readily compare such a data set (e.g., on a screen of a generic computer) to reference (e.g., historical) data (e.g., on a screen of a generic computer), to determine whether data features are present/absent relative to one another, and furthermore, could readily link such a contamination identification to a processing step (as ‘linking’ is not particularly limited, nor is linking, e.g., by speculation or based on ordinary knowledge, as an ordinarily skilled artisan would be readily apprised of possible contamination sources). Accordingly, the claim recites at least a mental processing grouping judicial exception, as well as reciting mathematical concepts (See MPEP 2106.04(a)(2).I) as the method amounts to merely reading in data, performing calculations on input data (e.g., partial additions, comparisons, unions, etc.), and making a judgement based thereon. The presence of contamination in such map data is a mathematical fact, and generally determining (according to some threshold, as would be known by an ordinarily skilled artisan) such data can be performed by generic mathematical calculations. Similarly, combining data sets from existing data sets and comparing data sets to one another can be performed by generic mathematical calculations (e.g., adding, subtracting, determining unions, determining various statistics of the sets, etc.). Linking is not particularly limited, and as such, linking is broad enough to include e.g., assigning data sets with particular determined data features (e.g., appeared vs. disappeared) relative to the historical data to particular result files associated with the particular type of feature (or to particular result files associated with particular processing steps) would read on the claim, which clearly can be performed by generic mathematical calculations and generic computer processing operations. Claim 23 recites similar limitations for a computer program product. Accordingly, at least claims 1, 14, 16, and 23 recite judicial exceptions. In step 2A, prong two (MPEP 2106.04.II.A.2), the inquiry asks whether the claims recite additional elements that integrate the judicial exception into a practical application. Claims 1-9, 11-13 do not have additional elements that integrate the judicial exception into a practical application, as they merely recite/further expand on portions of the judicial exception with additional data analysis/manipulation steps (claims 1, 5, 7, 11), or recite field of use/insignificant extra-solution activity steps (2-4, 6-9, 12-13). Additionally, there is no particular machine necessary to perform such steps. Furthermore, the judicial exception is not used to take any tangible action in the claims. Similarly, claim 14 recites no additional elements that integrate the judicial exception into a practical application, as it merely additionally recites generic computer processing/storage elements. Claims 16-18 and 20-22 also do not recite additional elements that integrate the judicial exception into a practical application, as they merely recite/further expand on portions of the judicial exception with additional data analysis/manipulation steps (claims 16, 20-21), or recite field of use/insignificant extra-solution activity steps (17-18, 22). Additionally, there is no particular machine necessary to perform such steps. Furthermore, the judicial exception is not used to take any tangible action in the claims. Similarly, claim 14 recites no additional elements that integrate the judicial exception into a practical application, as it merely additionally recites generic computer processing/storage elements. Similarly, claim 23 recites no additional elements that integrate the judicial exception into a practical application, as it merely additionally recites generic computer processing/storage elements. Under step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because no particular machine is required for any such method as presently claimed, and the only additional elements recited in the claims are those discussed in step 2A, prong two, which are all generic elements/field of use, and thus cannot amount to significantly more than the judicial exception. As such, claims 1-9, 11-14, 16-18, and 20-23 are rejected under 35 U.S.C. 101 as being patent ineligible as presently claimed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-9, 11-12, 14, 16-17, and 19-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Rhee (U.S. PGPub. No. US 20040239905 A1). Examiner notes that Van Rhee is Applicant provided prior art via the IDS dated 01/18/2023. Regarding claim 1, Van Rhee teaches a method for identifying contamination in a semiconductor fab ([0028]), the method comprising: determining contamination map data for each of a plurality of substrates clamped to a substrate table after being processed in the semiconductor fab ([0028]; [0068]); determining combined contamination map data based, at least in part, on a combination of the contamination map data of the plurality of substrates ([0068]), the combined contamination map data being a data set different than the respective contamination map data of each of the plurality of substrates ([0068]; Examiner notes that as discussed above, the combined contamination map data would be different than any particular respective contamination map data, and additionally, that retaining relative information from several previous samples would be different than the respective maps as well); and comparing the combined contamination map data to reference data ([0068]), wherein the reference data comprises one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab and comprises data associated with a previous processing stage ([0028]; [0068]). Regarding claim 2, Van Rhee teaches the method according to claim 1. Van Rhee further teaches wherein the contamination map data is determined based on data obtained by a levelling sensor (Abstract; [0051]-[0054]). Regarding claim 3, Van Rhee teaches the method according to claim 1. Van Rhee further teaches wherein the contamination map data comprises focus spot data ([0028]). Regarding claim 4, Van Rhee teaches the method according to claim 1. Van Rhee further teaches wherein the contamination map data is determined based on applying a spot detection algorithm to substrate height data ([0055]). Regarding claim 5, Van Rhee teaches the method according to claim 1. Van Rhee further teaches wherein the determining the combined contamination map data comprises determining a union of the contamination map data for the plurality of substrates ([0014]-[0017]; [0068]). Regarding claim 6, Van Rhee teaches the method according to claim 1. Van Rhee further teaches wherein the reference data comprises data indicative of failure of one or more dies in one or more substrates in the semiconductor fab ([0014]-[0017]; [0062]). Regarding claim 7, as best understood in view of the 35 U.S.C. 112(b) issues identified above, Van Rhee teaches the method according to claim 6. Van Rhee further teaches wherein the reference data comprises a focus error threshold, and wherein combined contamination map data above the focus error threshold is indicative of failure of the one or more dies in the one or more substrates in the semiconductor fab ([0014]-[0017]; [0062]). Regarding claim 8, Van Rhee teaches the method according to claim 1. Van Rhee further teaches wherein the reference data comprises geometry data relating to one or more tools in the semiconductor fab ([0068]; Examiner notes the disclosed position data are interpreted as geometry data). Regarding claim 9, Van Rhee teaches the method according to claim 8. Van Rhee further teaches wherein the geometry data comprises a position of one or more substrate support features of the one or more tools ([0068]). Regarding claim 11, Van Rhee teaches the method according to claim 8. Van Rhee further teaches further comprising determining, based on the comparison of the combined contamination map data to the geometry data of the one or more tools, one or more parts of the one or more tools or tool types in the semiconductor fab that are potential causes of contamination ([0068]). Regarding claim 12, Van Rhee teaches the method according to claim 1. Van Rhee further teaches wherein the plurality of substrates comprise substrates having, at least partially, a common fab context, wherein the fab context comprises one or more selected from: a product fabricated on the substrates, a layer of device structure fabricated on the substrates, a lithographic apparatus that has fabricated a device structure on the substrates, a time period during which the substrates have been processed, at least partially, in the semiconductor fab and/or a path that the substrates have taken through the semiconductor fab ([0028]). Regarding claim 14, Van Rhee teaches a computer program product comprising a non-transitory computer-readable medium having instructions therein, the instructions, when executed on at least one processor, cause the at least one processor to control an apparatus ([0080]) to at least: determine contamination map data for each of a plurality of substrates clamped to a substrate table after being processed in a semiconductor fab ([0028]; [0068]); determine combined contamination map data based, at least in part, on a combination of the contamination map data of the plurality of substrates ([0068]), the combined contamination map data being a data set different than the respective contamination map data of each of the plurality of substrates ([0068]; Examiner notes that as discussed above, the combined contamination map data would be different than any particular respective contamination map data, and additionally, that retaining relative information from several previous samples would be different than the respective maps as well); and comparing the combined contamination map data to reference data ([0068]), wherein the reference data comprises one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab and comprises data associated with a previous processing stage ([0028]; [0068]). Regarding claim 16, Van Rhee teaches a method for identifying contamination in a semiconductor fab (Abstract; [0028]), the method comprising: determining contamination map data obtained after processing in the semiconductor fab of a layer of a substrate ([0028]; [0068]); comparing the determined contamination map data with a previously obtained contamination map related to the semiconductor fab, to identify one or more contamination spots that have appeared since the previous contamination map or to identify one or more contamination spots that have disappeared since the previous contamination map ([0028]; [0068]); and linking the identification of the one or more contamination spots with a step identified from among a plurality of steps in the processing of the semiconductor fab ([0003]-[0012]; [0068]; Examiner notes that Van Rhee identifies second object table interacting with the samples from various other disclosed steps, and links the identification of contamination spots thereto). Regarding claim 17, Van Rhee teaches the method according to claim 16. Van Rhee further teaches wherein the contamination map data is determined based on data obtained by a level sensor (Abstract; [0051]-[0054]). Regarding claim 20, Van Rhee teaches the method according to claim 16. Van Rhee further teaches wherein the comparing comprises assigning a probability as to whether an identified contamination spot is a consequence of contamination introduced during processing of the semiconductor fab ([0028]; [0059]-[0068]; Examiner interprets assigning a likelihood as reading on assigning a probability, and interprets determining which spots are due to systemic contamination and which are not as assigning a probability as to whether an identified contamination spot is a consequence of processing contamination as well, i.e., by assigning a probability of 1 or 0). Regarding claim 21, as best understood in view of the 35 U.S.C. 112(b) issues identified above, Van Rhee teaches the method according to claim 16. Van Rhee further teaches wherein the identifying and linking is performed for a predefined sub-region of the substrate ([0028]; [0030]; [0052]-[0055]; [0059]-[0062]; [0068]). Regarding claim 22, Van Rhee teaches the method according to claim 16. Van Rhee further teaches wherein the contamination map data comprises focus spot data ([0028]). Regarding claim 23, Van Rhee teaches a computer program product comprising a non-transitory computer-readable medium having instructions therein, the instructions, when executed on at least one processor, cause the at least one processor to control an apparatus ([0080]) to at least: determine contamination map data obtained after processing in the semiconductor fab of a layer of a substrate ([0028]; [0068]); compare the determined contamination map data with a previously obtained contamination map related to the semiconductor fab, to identify one or more contamination spots that have appeared since the previous contamination map or to identify one or more contamination spots that have disappeared since the previous contamination map ([0028]; [0068]); and linking the identification of the one or more contamination spots with a step identified from among a plurality of steps in the processing of the semiconductor fab ([0003]-[0012]; [0068]; Examiner notes that Van Rhee identifies second object table interacting with the samples from various other disclosed steps, and links the identification of contamination spots thereto). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Van Rhee (U.S. PGPub. No. US 20040239905 A1) in view of Willis (U.S. PGPub. No. US 20080077362 A1). Regarding claim 13, as best understood in view of the 35 U.S.C. 112(b) issues identified above, Van Rhee teaches the method according to claim 1. Van Rhee does not explicitly teach wherein the reference data comprises data associated with a different semiconductor fab. Willis teaches wherein the reference data comprises data associated with a different semiconductor fab ([0083]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Van Rhee to include wherein the reference data comprises data associated with a different semiconductor fab, as taught by Willis. Doing so would allow one to, as taught by Willis, use historical data to determine whether particular wafers can be used. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Van Rhee (U.S. PGPub. No. US 20040239905 A1) in view of Cekli (WIPO Doc. No. WO 2015104074 A1). Regarding claim 18, Van Rhee teaches the method according to claim 16. Van Rhee does not explicitly teach wherein the previously obtained contamination map is a map obtained after processing of a previous layer of the same substrate. Cekli teaches wherein the previously obtained contamination map is a map obtained after processing of a previous layer of the same substrate (Abstract; [0057]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Van Rhee to include wherein the previously obtained contamination map is a map obtained after processing of a previous layer of the same substrate, as taught by Cekli. Doing so represents combining know prior art techniques according to known methods in order to achieve predictable results, and would allow one to determine displacements between successive layers in order to mitigate/prevent overlay errors, which would be useful for the invention of Van Rhee to ensure that successive wafers are positioned equivalently in order to ensure proper identification of overlapping focus spot, or to allow Van Rhee to perform the same technique between successive layers of the same sample. For completeness, Examiner notes that an ordinary skilled artisan would know that in real practice, samples are often multi-layered and would be reasonably apprised of the problem of overlay errors and would seek to mitigate the effects thereof. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Ypma’015 (US 20180253015 A1); Hauptmann (US 20170363969 A1); Inoue (US 20170069111 A1); Kawabata (US 20150221077 A1); Ypma’216 (US 20180307216 A1); Tsiatmas (US 20190243253 A1); Urbanczyk (US 20180217508 A1); Van Oosten (US 20210041788 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J GASSEN whose telephone number is (571)272-4363. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROBERT H KIM can be reached at (571)272-2293. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER J GASSEN/Examiner, Art Unit 2881 /DAVID E SMITH/Examiner, Art Unit 2881
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Prosecution Timeline

Jan 18, 2023
Application Filed
Jun 02, 2025
Non-Final Rejection mailed — §101, §102, §103
Oct 29, 2025
Response Filed
Jan 15, 2026
Final Rejection mailed — §101, §102, §103
Jul 15, 2026
Request for Continued Examination
Jul 17, 2026
Response after Non-Final Action
Aug 13, 2026
Non-Final Rejection mailed — §101, §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
99%
With Interview (+25.0%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 137 resolved cases by this examiner. Grant probability derived from career allowance rate.

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