DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 10/29/2025 have been entered. Claim 10 has been canceled. Claim 22 has been added. Claims 1-9, 11-14, and 16-22 are now pending in the application.
Response to Arguments
Applicant’s amendments to the claims have overcome each and every objection previously set forth in the Non-Final Office Action dated 06/02/2025, hereinafter NFOA0602.
Applicant’s amendments to the claims have overcome some of the 35 U.S.C. 112(b) rejections previously set forth in NFOA0602. While Examiner views Applicant’s response as bona fide, some issues were not ameliorated, and Applicant’s amendments have introduced additional issues. See 35 U.S.C. 112(b) section below for further discussion.
Applicant's arguments filed 10/29/2025 have been fully considered but they are not persuasive.
First, Applicant argues in regards to claim 1 (see Remarks pgs. 6-7), arguing that the cited portions of the prior art Van Rhee do not properly disclose the necessary limitations of the claim. Applicant argues “…paragraph [0068] of Van Rhee describes comparing a height map of one substrate with a height map of another substrate. But it is not apparent in what manner paragraph [0068] of Van Rhee describes a combination of contamination map data from a plurality of substrates and that combination being compared to reference data.” (Emphases added by Applicant).
Examiner respectfully disagrees that this differentiates between the requirements of the claim and the cited portions of Van Rhee.
Under the broadest reasonable interpretation (BRI), claim 1 requires:
determining contamination map data for each of a plurality of substrates clamped to a substrate table after being processed in the semiconductor fab
determining combined contamination map data
the combined contamination map data being based at least in part on a combination of the contamination map data of the plurality of substrates
comparing the combined contamination map data to reference data
the reference data including one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab
the reference data including data associated with a previous processing stage.
Van Rhee clearly discloses (i) in [0028] and [0068], which Applicant has not specifically refuted, and thus Examiner maintains.
In regards to (ii), Examiner first notes that the actual process/manner of combining the contamination map data of the plurality of substrates is not limited in the claim. Accordingly, any ‘combination’ of such data reads on the limitation, such as merely storing such data in a common location or including the data in a common repository to be called up for comparison. Paragraph [0068] discusses comparing maps of successive substrates (i.e., samples) to determine correlations of faults between the samples to indicate a source of contamination in the system, which would inherently require retaining the data for each of the maps such that each new map can be compared thereto. While Van Rhee does not explicitly discuss ‘combining’ each of the contamination maps into ‘combined contamination map data’, Van Rhee clearly teaches to compare the maps for each of the substrates to the previously measured maps (i.e., a set of historical data comprising the previous maps), and in particular to include comparing to maps other than the immediately preceding map (i.e., the threshold level is not particularly limited). In other words, in Van Rhee, a collection of historical data (i.e., a collection of maps) is maintained and added to in order to compare each successive measured map to, thus allowing one to count the focus spots on a same position to determine if the number of focus spots exceeds a threshold. It is Examiner’s opinion that an ordinarily skilled artisan would understand a set of previously measured maps, which are to be each compared to a particular map, as reading on combined contamination data, as it represents the same information, regardless of the particular phrasing used by Van Rhee. Under the BRI comparing a series of successive maps and retaining relative information between each of the maps could also be interpreted as combining the map data (but obviously would not read on combining the maps themselves, which is not required by the claim).
For completeness, Examiner notes that the claim does not require that each of the measured maps be combined into a single combined contamination map including all of the information contained in previously measured maps, and merely requires ‘determining combined contamination map data’, but does not limit how the data is ‘combined’, which is broad enough to include various means and degrees of ‘combination’, nor how much/what portion(s) of the data need be combined. Examiner also notes that an ordinarily skilled artisan could also readily combine any number of historical data sets of the same kind (e.g., contamination maps) to form a single composite data set using solely their ordinary skill and conventional techniques.
Accordingly, under the BRI, it remains Examiner’s opinion that the cited portions of Van Rhee read on the requirements of this portion of the claim.
In regards to (iii), the combined contamination map data is required to be compared to reference data, where the reference data is ‘one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab’ and ‘data associated with a previous processing stage’. However, Examiner notes that the claim does not limit how this comparison must be performed, nor what elements of the combined contamination map data and reference data are required to be compared, nor does it limit the reference data to preclude the combined contamination map data itself or elements thereof.
In Van Rhee, each successive map taken becomes a part of the combined contamination map data for comparison to additional successive maps. This combined contamination map data could, itself, also be reasonably interpreted as reference data (or at least the portion which is not the ‘most recent’ map). Thus, under the BRI, the ‘most recent’ map is compared with historical maps, which reads on comparing the combined contamination map data to reference data. The claim does not preclude this arrangement disclosed by Van Rhee, in which each new portion of the combined contamination map data (i.e., each new map) is compared to previous historical data sets (i.e., the set of previous maps, which is interpreted as reference data), wherein the previous historical data sets (i.e., reference data) include ‘one or more values indicative of contamination in one or more tools in the semiconductor fab’ (i.e., focus/chuck spots associated with an object table) and ‘data associated with a previous processing stage’ (i.e., the historical maps). Accordingly, under the BRI, it remains Examiner’s opinion that the cited portions of Van Rhee read on the requirements of this portion of the claim.
Accordingly, under the BRI, the cited portions of Van Rhee read on each and every required limitation of claim 1, and Examiner maintains the rejection as proper.
Next, Applicant argues in regards to claim 16 (see Remarks pgs. 7-8), arguing that the cited portions of the prior art Van Rhee do not properly disclose the necessary limitations of the claim. Applicant argues “…the cited portions of Van Rhee describe a comparison of an identified measured focus spot / unflatness on one substrate with an identified measured focus spot / unflatness on another substrate. Thus, it is not apparent that the cited portions of Van Rhee describe identifying the appearance of a contamination spot since a previous contamination map or a disappearance of a contamination spot since a previous contamination map, as claimed. Instead, the focus spot / unflatness is always identified in the previous and subsequent measured data.” (Emphases added by Applicant).
Examiner respectfully disagrees that this differentiates between the requirements of the claim and the cited portions of Van Rhee.
Under the BRI, claim 16 requires:
determining contamination map data obtained after processing in the semiconductor fab of a layer of a substrate
comparing the determined contamination map data with a previously obtained contamination map related to the semiconductor fab
identifying one or more contamination spots that have
appeared since the previous contamination map
disappeared since the previous contamination map
[only (iii).a or (iii).b is required]
linking the identification of the one or more contamination spots with a step in the processing of the semiconductor fab.
Van Rhee clearly discloses (i) and (ii) in [0028] and [0068], which Applicant has not specifically refuted and thus Examiner maintains, and also discloses (iv) in [0068], which Applicant also has not specifically refuted and thus Examiner also maintains.
In regards to (iii), Van Rhee discloses “When the number of focus spots on the same position on successive wafers exceeds a certain threshold level, it will then be considered a chuck spot.”, which one of ordinary skill in the art would understand to mean both that when the number of focus spots on the same position of successive wafers does exceed the threshold, it will be considered a chuck spot, and that when the number of focus spots on the same position of successive wafers does not exceed the threshold, it will not be considered a chuck spot. However, the threshold can be arbitrarily set, and focus spots can occur (and in a real system will occur) without indicating the presence of a chuck spot. Furthermore, were focus spots to appear on a sub-threshold number of successive wafers, an ordinarily skilled artisan would understand that such a focus spot would either appear or disappear relative to the preceding or following wafers. Van Rhee at no point requires that each successive wafer have overlapping focus spots between each wafer, only that if a sufficient number of wafers do have overlapping focus spots, then a chuck spot is identified. Obviously in real operation there will not always be a chuck spot found, and in cases in which a chuck spot is not found despite focus spots appearing in one or more of the individual wafer maps, the focus spot will necessarily appear or disappear. While Van Rhee does not use the same wording, it describes equivalent functionality for the same purpose: comparing contamination maps of wafers to previous contamination maps to determine whether systemic faults are present in the fab.
Examiner notes for completeness that an ordinarily skilled artisan in the field of such lithography application will typically have a post-graduate degree and have significant experience and education within the field of semiconductor fabrication, and would thus also know and understand how such a situation of a sub-threshold number of successive focus spot appearing in contamination maps would/could occur, absent any teaching from Van Rhee or other prior art.
Finally, Examiner additionally notes for completeness that as discussed in [0056]-[0066], for each wafer focus spots are determined with (x,y)-coordinate locations, meaning that the user will have access to the location of any identified focus spots of each of the measured wafers. Van Rhee additionally discloses in [0063] and [0073]: “a reporting system arranged to report focus spots, for example to a user” and “the reporting system and the processor are arranged to report different classifications of focus spots” and “If relatively large focus spots occur, they may cause processing to immediately cease, while smaller focus spots only need to be reported, in for example an administration file”, which indicates not only the ability to identify and locate focus spots, but also to classify and take action based on such identification and classification. Given the information on the location of focus spots between successive samples, and the instruction to compare the location of such focus spots between successive samples, one of ordinary skill in the art could also readily determine whether a focus spot has appeared or disappeared between any two of such samples by mere inspection.
Accordingly, under the BRI, the cited portions of Van Rhee read on each and every required limitation of claim 16, and Examiner maintains the rejection as proper.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 21 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, as discussed in NFOA0602, the claim was rendered indefinite for similar reasons to those of previous claim 6 and was interpreted similarly for purposes of examination. The previous issue of claim 7 was not ameliorated. Claim 7 recites “the one or more dies in the one or more subsequent substrates”, which is indefinite because it is unclear what ‘subsequent’ is intended to indicate in this context, as previously discussed. As such, it is not possible to adequately determine the metes and bounds of the claim, rendering it indefinite. For purposes of examination, this limitation is interpreted as ‘one or more dies in the one or more substrates in the semiconductor fab’.
Claim 21 recites “wherein the identifying and linking of a contamination spot is performed for a predefined sub-region of the substrate”. However, claim 16 refers to ‘identify[ing] one or more contamination spots’ and ‘linking the identification of the one or more contamination spots with…’, but does not refer to any particular contamination spot. As such, it is unclear whether ‘a contamination spot’ is intended to refer to one of the ‘one or more contamination spots’, as claim 16 only refers to identifying and linking these ‘one or more contamination spots’. As such, it is not possible to adequately determine the metes and bounds of the claim, rendering it indefinite. For purposes of examination, this limitation is interpreted as ‘wherein the identifying and linking of the one or more contamination spots is performed for a predefined sub-region of the substrate’.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 11-12, 14, 16-17, and 19-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Rhee (U.S. PGPub. No. US 20040239905 A1).
Examiner notes that Van Rhee is Applicant provided prior art via the IDS dated 01/18/2023.
Regarding claim 1, Van Rhee teaches a method for identifying contamination in a semiconductor fab ([0028]), the method comprising:
determining contamination map data for each of a plurality of substrates clamped to a substrate table after being processed in the semiconductor fab ([0028]; [0068]);
determining combined contamination map data based, at least in part, on a combination of the contamination map data of the plurality of substrates ([0068]); and
comparing the combined contamination map data to reference data ([0068]), wherein the reference data comprises one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab and comprises data associated with a previous processing stage ([0028]; [0068]).
Regarding claim 2, Van Rhee teaches the method according to claim 1.
Van Rhee further teaches wherein the contamination map data is determined based on data obtained by a levelling sensor (Abstract; [0051]-[0054]).
Regarding claim 3, Van Rhee teaches the method according to claim 1.
Van Rhee further teaches wherein the contamination map data comprises focus spot data ([0028]).
Regarding claim 4, Van Rhee teaches the method according to claim 1.
Van Rhee further teaches wherein the contamination map data is determined based on applying a spot detection algorithm to substrate height data ([0055]).
Regarding claim 5, Van Rhee teaches the method according to claim 1.
Van Rhee further teaches wherein the determining the combined contamination map data comprises determining a union of the contamination map data for the plurality of substrates ([0014]-[0017]; [0068]).
Regarding claim 6, Van Rhee teaches the method according to claim 1.
Van Rhee further teaches wherein the reference data comprises data indicative of failure of one or more dies in one or more substrates in the semiconductor fab ([0014]-[0017]; [0062]).
Regarding claim 7, as best understood in view of the 35 U.S.C. 112(b) issues identified above, Van Rhee teaches the method according to claim 6.
Van Rhee further teaches wherein the reference data comprises a focus error threshold, and wherein combined contamination map data above the focus error threshold is indicative of failure of the one or more dies in the one or more [in the semiconductor fab] ([0014]-[0017]; [0062]).
Regarding claim 8, Van Rhee teaches the method according to claim 1.
Van Rhee further teaches wherein the reference data comprises geometry data relating to one or more tools in the semiconductor fab ([0068]; Examiner notes the disclosed position data are interpreted as geometry data).
Regarding claim 9, Van Rhee teaches the method according to claim 8.
Van Rhee further teaches wherein the geometry data comprises a position of one or more substrate support features of the one or more tools ([0068]).
Regarding claim 11, Van Rhee teaches the method according to claim 8.
Van Rhee further teaches further comprising determining, based on the comparison of the combined contamination map data to the geometry data of the one or more tools, one or more parts of the one or more tools or tool types in the semiconductor fab that are potential causes of contamination ([0068]).
Regarding claim 12, Van Rhee teaches the method according to claim 1.
Van Rhee further teaches wherein the plurality of substrates comprise substrates having, at least partially, a common fab context, wherein the fab context comprises one or more selected from: a product fabricated on the substrates, a layer of device structure fabricated on the substrates, a lithographic apparatus that has fabricated a device structure on the substrates, a time period during which the substrates have been processed, at least partially, in the semiconductor fab and/or a path that the substrates have taken through the semiconductor fab ([0028]).
Regarding claim 14, Van Rhee teaches a computer program product comprising a non-transitory computer-readable medium having instructions therein, the instructions, when executed on at least one processor, cause the at least one processor to control an apparatus ([0080]) to at least:
determine contamination map data for each of a plurality of substrates clamped to a substrate table after being processed in a semiconductor fab ([0028]; [0068]);
determine combined contamination map data based, at least in part, on a combination of the contamination map data of the plurality of substrates ([0068]); and
comparing the combined contamination map data to reference data ([0068]), wherein the reference data comprises one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab and comprises data associated with a previous processing stage ([0028]; [0068]).
Regarding claim 16, Van Rhee teaches a method for identifying contamination in a semiconductor fab (Abstract; [0028]), the method comprising:
determining contamination map data obtained after processing in the semiconductor fab of a layer of a substrate ([0028]; [0068]);
comparing the determined contamination map data with a previously obtained contamination map related to the semiconductor fab, to identify one or more contamination spots that have appeared since the previous contamination map or to identify one or more contamination spots that have disappeared since the previous contamination map ([0028]; [0068]); and
linking the identification of the one or more contamination spots with a step in the processing of the semiconductor fab ([0008]; [0068]).
Regarding claim 17, Van Rhee teaches the method according to claim 16.
Van Rhee further teaches wherein the contamination map data is determined based on data obtained by a level sensor (Abstract; [0051]-[0054]).
Regarding claim 19, Van Rhee teaches the method according to claim 16.
Van Rhee further teaches wherein the previously obtained contamination map is a map obtained after processing of the same layer of another substrate ([0028]; [0068]).
Regarding claim 20, Van Rhee teaches the method according to claim 16.
Van Rhee further teaches wherein the comparing comprises assigning a probability as to whether an identified contamination spot is a consequence of contamination introduced during processing of the semiconductor fab ([0028]; [0059]-[0068]; Examiner interprets assigning a likelihood as reading on assigning a probability, and interprets determining which spots are due to systemic contamination and which are not as assigning a probability as to whether an identified contamination spot is a consequence of processing contamination as well, i.e., by assigning a probability of 1 or 0).
Regarding claim 21, as best understood in view of the 35 U.S.C. 112(b) issues identified above, Van Rhee teaches the method according to claim 16.
Van Rhee further teaches wherein the identifying and linking of [the one or more contamination spots] is performed for a predefined sub-region of the substrate ([0028]; [0030]; [0052]-[0055]; [0059]-[0062]; [0068]).
Regarding claim 22, Van Rhee teaches the method according to claim 16.
Van Rhee further teaches wherein the contamination map data comprises focus spot data ([0028]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Van Rhee (U.S. PGPub. No. US 20040239905 A1) in view of Willis (U.S. PGPub. No. US 20080077362 A1).
Regarding claim 13, as best understood in view of the 35 U.S.C. 112(b) issues identified above, Van Rhee teaches the method according to claim 1.
Van Rhee does not explicitly teach wherein the reference data comprises data associated with a different semiconductor fab.
Willis teaches wherein the reference data comprises data associated with a different semiconductor fab ([0083]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Van Rhee to include wherein the reference data comprises data associated with a different semiconductor fab, as taught by Willis.
Doing so would allow one to, as taught by Willis, use historical data to determine whether particular wafers can be used.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Van Rhee (U.S. PGPub. No. US 20040239905 A1) in view of Cekli (WIPO Doc. No. WO 2015104074 A1).
Regarding claim 18, Van Rhee teaches the method according to claim 16.
Van Rhee does not explicitly teach wherein the previously obtained contamination map is a map obtained after processing of a previous layer of the same substrate.
Cekli teaches wherein the previously obtained contamination map is a map obtained after processing of a previous layer of the same substrate (Abstract; [0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Van Rhee to include wherein the previously obtained contamination map is a map obtained after processing of a previous layer of the same substrate, as taught by Cekli.
Doing so represents combining know prior art techniques according to known methods in order to achieve predictable results, and would allow one to determine displacements between successive layers in order to mitigate/prevent overlay errors, which would be useful for the invention of Van Rhee to ensure that successive wafers are positioned equivalently in order to ensure proper identification of overlapping focus spot, or to allow Van Rhee to perform the same technique between successive layers of the same sample. For completeness, Examiner notes that an ordinary skilled artisan would know that in real practice, samples are often multi-layered and would be reasonably apprised of the problem of overlay errors and would seek to mitigate the effects thereof.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J GASSEN whose telephone number is (571)272-4363. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROBERT H KIM can be reached at (571)272-2293. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER J GASSEN/ Examiner, Art Unit 2881
/MICHAEL J LOGIE/ Primary Examiner, Art Unit 2881