DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 6-7, 9-17, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Appl. Publ. No. 2009/0314205 to Patalay, et al. (hereinafter “Patalay”) in view of U.S. Patent Appl. Publ. No. 2003/0143410 to Won, et al. (“Won”).
Regarding claim 6, Patalay teaches an apparatus for depositing a layer of semiconductor material on a substrate wafer (see the Abstract, Figs. 1-5, and entire reference) comprising:
an upper cover and a lower cover defining a reactor chamber (see Fig. 1 and ¶¶[0034]-[0038] which teach an upper quartz window (107) and lower quartz window (108));
a base ring disposed between the upper and lower covers (see Fig. 1 and ¶¶[0034]-[0038] which teach a base ring (106) which includes components disposed between windows (107) and (108));
a carrier to hold the substrate wafer during the deposition of the layer (see Fig. 1 and ¶¶[0034]-[0038] which teach a susceptor (102) to hold a substrate);
a gas inlet and a gas outlet to pass process gas over an upper side of the substrate wafer (see Fig. 1 and ¶¶[0034]-[0038] which teach a gas inlet (110) and outlet (111));
a slit valve tunnel and a slit valve door (see Fig. 1 and ¶¶[0034]-[0038] which specifically teach that he internal volume (109) is closed off by a slit valve and slit valve opening (not shown)); and
a rotating lift to lift and turn the carrier and the substrate wafer (see Fig. 1 and ¶¶[0034]-[0038] which teach a support structure (118) which is capable of lifting and rotating the susceptor (102) and substrate),
wherein one or more components include stainless steel (see at least ¶[0045] which teaches the use of a stainless tube for temperature measurement which is understood to mean stainless steel; moreover, stainless steel is ubiquitous in the microelectronics industry and a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to construct one or more components such as the base ring, gas inlet and outlet, and slit valve from a material such as stainless steel in order to benefit from its high strength, high operating temperatures, and corrosion resistance).
Patalay does not teach that a coating including silicon and hydrogen is disposed on one or more of the stainless steel components. However, in Figs. 2-3 and ¶¶[0030]-[0037] as well as elsewhere throughout the entire reference Won teaches an analogous system and method for film growth by chemical vapor deposition (CVD) from gaseous precursors. In ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay with a layer of a-Si:H in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus. The combination of prior art elements according to known methods to yield predictable results has been held to support a prima facie determination of obviousness. All the claimed elements are known in the prior art and one skilled in the art could combine the elements as claimed by known methods with no change in their respective functions, with the combination yielding nothing more than predictable results to one of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S. 398, __, 82 USPQ2d 1385, 1395 (2007). See also, MPEP 2143(A).
Regarding claim 7, Patalay does not teach that the coating is an amorphous silicon or a functionalized silicon coating thereon. However, as noted supra with respect to the rejection of claim 6, in ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay with a layer of a-Si:H in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus.
Regarding claim 9, Patalay teaches a gas supply line and outgoing gas line (see Fig. 1 and ¶¶[0034]-[0038] which teach a gas inlet (110) and outlet (111) which are connected to a gas supply line and outgoing gas line, respectively).
Regarding claim 10, Patalay does not teach that the gas supply line is coated with the coating. However, as noted supra with respect to the rejection of claim 6, in ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay, including at least a portion of the gas supply and outgoing gas lines with a layer of a-Si:H in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus. Moreover, it is noted that the process of coating the chamber interior itself will necessarily cause at least a portion of the gas supply and outgoing gas lines to be coated with the desired coating.
Regarding claim 11, Patalay does not teach that the outgoing gas line is coated with the coating. However, as noted supra with respect to the rejection of claim 6, in ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay, including at least a portion of the gas supply and outgoing gas lines with a layer of a-Si:H in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus. Moreover, it is noted that the process of coating the chamber interior itself will necessarily cause at least a portion of the gas supply and outgoing gas lines to be coated with the desired coating.
Regarding claim 12, Patalay does not teach that the one or more components includes one or more of the upper cover, the lower cover, the base ring, the gas inlet, the gas outlet, the gas supply line, the outgoing gas line, the slit valve tunnel, a slit valve door, and the rotating lift. However, as noted supra with respect to the rejection of claim 6, in ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay including, for example, the upper and lower covers, the base ring, the gas inlet and outlet, and the rotating lift with a layer of a-Si:H in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus. Moreover, it is noted that the process of coating the chamber interior itself will necessarily cause at least a portion of the recited components to be coated with the desired coating.
Regarding claim 13, Patalay teaches that the reactor chamber is configured as a single-wafer reactor (see Fig. 1 and ¶¶[0034]-[0038] which teach that the support structure (118) is configured to lift and rotate a susceptor (102) carrying a single wafer).
Regarding claim 14, Patalay teaches that the upper and lower covers are respectively upper and lower domes (see Fig. 1 and ¶¶[0034]-[0038] which teach an upper quartz window (107) and lower quartz window (108) which may be considered as upper and lower domes, respectively).
Regarding claim 15, Patalay teaches that the reactor is configured to deposit an epitaxial layer on the substrate wafer (see Fig. 1 and ¶[0033] which teach that the reactor is configured for epitaxial deposition onto a substrate wafer).
Regarding claim 16, Patalay does not teach that the amorphous silicon coating is present. However, as noted supra with respect to the rejection of claim 6, in ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay with a layer of a-Si:H in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus.
Regarding claim 17, Patalay does not teach that the amorphous silicon coating includes a composition represented by the formula a-Si:H. However, as noted supra with respect to the rejection of claim 6, in ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay with a layer of a-Si:H in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus.
Regarding claim 21, Patalay teaches that the carrier includes a susceptor (see Fig. 1 and ¶¶[0034]-[0038] which teach a susceptor (102) to hold a substrate).
Regarding claim 22, Patalay does not teach that the coating is applied by chemical vapor deposition. However, as noted supra with respect to the rejection of claim 6, in ¶¶[0008]-[0009] and ¶[0033] Won specifically teaches the desirability of conditioning or seasoning the interior of the CVD chamber by depositing a thin inactive film on interior surfaces prior to performing film growth in order to minimize contamination of the subsequently deposited thin film. In ¶¶[0034]-[0037] Won further teaches an embodiment in which interior surfaces are coated with a layer of hydrogenated amorphous silicon (a-Si:H) for this purposes using hydrogen (H2) and silane (SiH4) as process gases during CVD deposition. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Won and would be motivated to coat interior surfaces of the CVD apparatus of Patalay with a layer of a-Si:H by CVD in order to reduce the propensity for contamination of subsequently deposited thin films with material arising from interior surfaces of the CVD apparatus.
Regarding claim 23, Patalay teaches a method for depositing a layer on a substrate wafer, the method comprising:
providing the apparatus of claim 6; disposing the substrate wafer in the reactor chamber (see Fig. 1 and ¶¶[0034]-[0038] which teach disposing a wafer on the susceptor (102) located within the CVD growth apparatus (100)); and
depositing an epitaxial layer of semiconductor material on the substrate wafer (see specifically ¶¶[0005]-[0009] and ¶[0033] which teach methods in which epitaxial deposition is performed on the wafer).
Regarding claim 24, Patalay teaches that the epitaxial layer of semiconductor material is deposited on the substrate wafer at 1000 to 1300°C (see specifically ¶[0009] which teaches that epitaxial deposition is performed at temperatures from room temperature to about 1,200 °C).
Claims 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patalay in view of Won and further in view of Japanese Patent Appl. Publ. No. JP 2011-146596 A to Kawahara, et al. (“Kawahara”).
Regarding claim 8, Patay and Won do not teach that the functionalized silicon coating is present and includes a compositions represented by the formula a-SiOx:CHy. However, in Fig. 1 and the Description of Embodiments section at pp. 3-7 as well as elsewhere throughout the entire reference Kawahara teaches analogous system and method for the deposition of an organic silica film on a substrate in which a precoat film comprised of SiCOH is deposited on interior surface of the CVD chamber from precursors such as silane, TEOS, and an oxidizing gas. The SiCOH precoat layer is primarily used to reduce the time required to clean the chamber after film growth, but would also be reasonably expected to reduce the propensity for contaminants to become incorporated in the organic silica film as internal components are coated by the SiCOH layer before and during film growth. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to produce the hydrogenated amorphous silicon pre-coat layer of Won utilizing gaseous SiCOH precursors such that a functionalized Si coating comprised of a-SiOx:CHy is produced in order to promote ease of chamber cleaning after film growth and to reduce the propensity for contamination when depositing an organic silica film.
Regarding claim 18, Patalay and Won do not teach that the amorphous silicon coating includes a composition represented by the formula a-SixC1-x:H. However, as noted supra with respect to the rejection of claim 17, in Fig. 1 and the Description of Embodiments section at pp. 3-7 as well as elsewhere throughout the entire reference Kawahara teaches analogous system and method for the deposition of an organic silica film on a substrate in which a precoat film comprised of SiCOH is deposited on interior surface of the CVD chamber from precursors such as silane, TEOS, and an oxidizing gas. The SiCOH precoat layer is primarily used to reduce the time required to clean the chamber after film growth, but would also be reasonably expected to reduce the propensity for contaminants to become incorporated in the organic silica film as internal components are coated by the SiCOH layer before and during film growth. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to produce the hydrogenated amorphous silicon pre-coat layer of Won utilizing gaseous SiCOH precursors such that a Si coating comprised of a-SixC1-x:H is produced in order to promote ease of chamber cleaning after film growth and to reduce the propensity for contamination when depositing an organic silica film.
Claims 19-20 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patalay in view of Won and further in view of U.S. Patent Appl. Publ. No. 2006/0286774 to Singh, et al. (“Singh”).
Regarding claim 19, Patalay and Won do not teach that the substrate wafer has a diameter of at least 200 mm. However, in at least Fig. 4, ¶[0038], and ¶[0191] Singh teaches an analogous system and method for the growth of epitaxial Si layers onto one or more substrates. In ¶[0191] Singh specifically teaches that industry standard substrates may have a diameter of 200 or 300 mm. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Singh and would be motivated to configure the CVD apparatus of Patalay and Won for deposition onto substrates having a diameter of at least 200 mm in order to enable processing of industry-standard wafer sizes and to maximize the number of devices that may be formed per wafer.
Regarding claim 20, Patalay and Won do not teach that the substrate wafer has a diameter of at least 300 mm. However, in at least Fig. 4, ¶[0038], and ¶[0191] Singh teaches an analogous system and method for the growth of epitaxial Si layers onto one or more substrates. In ¶[0191] Singh specifically teaches that industry standard substrates may have a diameter of 200 or 300 mm. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Singh and would be motivated to configure the CVD apparatus of Patalay and Won for deposition onto substrates having a diameter of at least 300 mm in order to enable processing of industry-standard wafer sizes and to maximize the number of devices that may be formed per wafer.
Regarding claim 25, Patalay and Won do not teach that the substrate wafer and/or the epitaxial layer are doped with an electrically active dopant. However, in at least Fig. 4, ¶[0038], and ¶¶[0155]-[0158] Singh teaches an analogous system and method for the growth of epitaxial Si layers onto one or more substrates. In ¶¶[0155]-[0158] Singh specifically teaches that the substrate and/or the epitaxial layer may be doped with one or more electrically active dopant such as boron, arsenic, or phosphorous as part of a process for forming electronic devices thereupon. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to utilize a doped Si substrate and/or epitaxial layer as part of a process for forming one or more electronic devices thereupon.
Response to Arguments
Applicant's arguments filed October 30, 2025, have been fully considered, but they are not persuasive.
Applicant argues that Patalay does not disclose stainless steel components. See applicant’s’ 10/30/2025 reply, p. 5. This argument is not found persuasive as ¶[0045] of Patalay specifically teaches that temperatures were measured using a “stainless tube” with thermocouples. Stainless steel is well-known in the art due to its high temperature and corrosion-resistant properties and, consequently, the disclosure of a “stainless tube” would be understood by a person of ordinary skill in the art as a reference to the use of stainless steel. As written, claim 6 merely requires that “one or more components include stainless steel” and, as such, the use of a stainless tube meets the claim because it is a component that utilizes stainless steel.
Applicant then argues that the use of stainless steel is not ubiquitous in the art, that none of the cited reference disclose stainless steel components, that other materials other than stainless steel may be used, and that common sense cannot be used to supply a missing component. Id. at pp. 5-6. Applicant’s arguments are noted, but are persuasive since, for one, they are based on arguments of counsel rather than factually supported, objective evidence. Second, the Examiner notes that prior art is not limited to the references being applied, but includes the understanding of one of ordinary skill in the art. The “mere existence of differences between the prior art and an invention does not establish the invention’s nonobviousness.” Dann v. Johnston, 425 U.S. 219, 230, 189 USPQ 257, 261 (1976). See also MPEP 2141(III). Third, in ¶[0004] Won merely teaches that in some embodiments CVD chambers are made of aluminum, but this does not mean that all CVD chambers are made of aluminum or that other components such as the carrier to hold the substrate, gas inlets and outlets, and/or the rotating lift cannot or would not be made of stainless steel. In support of the Examiner’s position, reference is made to at least Figs. 8-9 and ¶[0205] of U.S. Patent Appl. Publ. No. 2006/0286774 to Singh, et al. (“Singh”) which teach, for example, that flow control ring (1142) may be made from a material compatible with the process conditions such as stainless steel.
Applicant argues that the Examiner’s position that the use of stainless steel would benefit from its high strength, high operating temperatures, and corrosion resistance is not gleaned from the prior art and relies on impermissible hindsight. See applicant’s’ 10/30/2025 reply, pp. 6-7. This argument is not found persuasive for reasons noted supra. In support of the Examiner’s position, references is made to at least Figs. 8-9 and ¶[0205] of Singh which teach, for example, that flow control ring (1142) may be made from a material compatible with the process conditions such as stainless steel. Similarly, in at least the fourth paragraph in the Background Art section, Japanese Patent Appl. Publ. No. JP2001-146596A to Kawahara, et al. teaches an embodiment in which the plasma reaction chamber inner wall in a CVD system is made from a conductive metal such as stainless steel.
Applicant then argues that Won does not teach or suggest depositing the amorphous silicon film on stainless steel and instead teaches that the aforementioned film is deposited on ceramic or anodized aluminum liners and there is no motivation to apply an amorphous silicon film to stainless steel components. Id. at pp. 7-9. This argument is not found persuasive since, for one, it amounts to arguing against the references individually. In this case, it is Patalay rather than Won that is relied upon to teach the use of one or more stainless steel components. Won is then introduced to teach a coating including silicon and hydrogen as claimed. Second, there is nothing in Won that specifically teaches that its chamber seasoning process can only be applied to aluminum or ceramic components. The step of avoiding or minimizing contamination by depositing a thin inactive film on interior surfaces may be utilized regardless of whether the chamber is constructed of aluminum, a ceramic, or stainless steel as each is comprised of materials that may function as a potential source of contaminants. In ¶[0034] Won specifically teaches that the “PECVD chamber was pretreated with an a-Si seasoning process” and does not specify that the chamber itself must be manufactured from a ceramic material or anodized aluminum. In fact, as detailed supra, at least the fourth paragraph in the Background Art section of Kawahara specifically teaches that the plasma reaction chamber inner wall in a CVD system is made from a conductive metal such as stainless steel.
Finally, applicant argues that there is no motivation to combine the thermal CVD technologies of Patalay with the plasma enhanced CVD system of Won due to the use of lower temperatures and an ionized gas in Won and higher temperatures in Patalay. Id. at p. 9. Applicant’s argument is noted, but is unpersuasive. The teachings of Patalay and Won both relate to thin film growth by CVD and, hence, are considered analogous art. The mere fact that Won utilizes a plasma does not mean that its teachings are not applicable to other CVD processes. The issue of contamination due to desorption or etching of atomic species from chamber walls is an issue that is common to all CVD processes and is not unique to plasma CVD because the chamber walls and other internal components are formed from elements other than what is being deposited as a thin film. By forming an internal surface coating of an inert material or of the same material that is being deposited it is possible to reduce the propensity for contamination of the deposited thin film because the atomic species that are being desorbed are of the same composition as and/or do not negatively affect the deposited film.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH A BRATLAND JR whose telephone number is (571)270-1604. The examiner can normally be reached Monday- Friday, 7:30 am to 4:30 pm EST.
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/KENNETH A BRATLAND JR/Primary Examiner, Art Unit 1714
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