Attorney’s Docket Number: 0118/0658PUS1
Filing Date: 02/08/2023
Claimed Priority Date: 12/23/2020(CN 202011540576.9)
11/16/2021(PCT/CN2021/130874)
Applicant: Yang
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the Amendment filed on 11/24/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 11/24/2025, responding to the Office action mailed on 08/27/2025, has been entered. Applicant cancelled claims 6-7 and amended claim 2. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 2-5,11-14.
Response to Amendment
Applicant amendments to the Claims have overcome the respective claim objections and the claim rejections under 35 U.S.C. 103 and 102, as previously formulated in the Non-Final Office action mailed on 07/28/2025. However, some of the previously presented prior art remains relevant, and new grounds for rejection are presented below, as necessitated by Applicant’s amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2,3,5 are rejected under 35 U.S.C. 103 as being unpatentable over Yim (US 20120129333 A1, Hereinafter Yim) in view of Burrell et al (US 20050074959 A1, Hereinafter Burrell) in view of Culverhouse Jr (US 2662831 A, Hereinafter Culverhouse)
Regarding claim 2, Yim (e.g., Fig 3A-3B, Fig1A-1F, 2 [0062]-[0066][0029]-[0052]) discloses most aspects of the instant invention, including, a manufacturing method for a die (e.g., [0030]), comprising:
providing a wafer (e.g., substrate 102 [0030]), the wafer comprising a passivation layer and a plurality of aluminum bonding pads (e.g., protection layer 106 and bonding pad 104, Fig 2 shows plurality) , the passivation layer and the plurality of aluminum bonding pads arranged on an active surface of the wafer, the passivation layer having a plurality of first openings in which the aluminum bonding pads are partially exposed (e.g., Fig 3A and [0032] “bonding pad 104 is exposed due to the lack of the protection layer 106”) ;
forming a patterned mask layer over the passivation layer and the plurality of aluminum bonding pads, the patterned mask layer having second openings in which the aluminum bonding pads are partially exposed (e.g., Fig 3A openings 110a and 110b), the patterned mask layer completely covering the passivation layer;
forming a copper layer in the second openings and removing the patterned mask layer (e.g., Fig 1C/1D plating films 120a);
and dicing the wafer into a plurality of dies (e.g., [0030])
While Yim shows the aluminum bond pads are exposed, it is silent about removing an oxide layer from the aluminum bonding pads.
Burrell (e.g., Fig 1G, [0044]), on the other hand and in a similar field of Al bondpads in an opening of passivation layer, teaches when Al surfaces are exposed, they tend to form native oxides on an upper surface. Burrell removes the native oxide using a micro-etch as a preferred clean/pretreatment step to ensure complete removal of native oxides.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the removal of oxide step prior to plating a metal on the exposed pads in the method of Yim, as taught by Burrell, to improve adhesion and protect the aluminum pads from future oxidation.
While Yim in shows a copper layer on a Al layer that has undergone oxide removal, it is silent about the copper layer being electroless plated using a zinc displacement reaction.
Culverhouse, (cols 1-4) on the other hand and in a related field of solving a problem of copper adhesion to Aluminum surfaces, teaches a method to chemically coat a cleaned Aluminum surface with copper using a displacement reaction with zinc (Col 2, lines 27-55). Culverhouse electrolessly plates a layer of zinc on the Aluminum by immersing it into a zincate solution, and then chemically replacing a zinc layer with copper by immersing the substrate into a copper fluoborite solution to form a uniform layer that does not blister or become separated from aluminum.
Accordingly, it would been obvious to form a electrolessly plated zinc layer in the second openings; and forming the copper layer by displacement of the zinc layer with copper, in the device of Yim/Burrell, as taught by Culverhouse, to obtain an “even and strongly adherent” coat of copper on the aluminum pad.
Regarding Claim 3, Yim (e.g., Fig 3A-3B, Fig1A-1F, 2 [0062]-[0066][0029]-[0052]) discloses an opening formed between the boundary of the copper layer (e.g., Fig 2/1F), however, it is silent about the distance being between 3um-10um.
Additionally, with regards to the particular range of opening width dimensions claimed, it is also noted that the specification fails to provide teachings about the criticality of having the opening distance to be between 3um-10um, and the courts have held that differences in (widths) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed range, and since Yim teaches a dimension known in the art, it would have been obvious to one of ordinary skill in the art to use a opening width in the range of 3um-10um.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed dimensions ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions ratios or upon another variable recited in a claim, the applicant must show that the chosen ratios are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Regarding claim 5, see comments from paragraph 6-8 from claim 2, as they would be considered repeated here.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yim/Burrell/Culverhouse further in view of Chen (US 6251804 B1, Hereinafter Chen).
Regarding claim 4, While Yim/Burrell/Culverhouse discloses a mask layer over a passivation layer, it is silent about a method wherein the passivation layer is bombarded by an oxygen or argon plasma prior to applying a photo resist.
Chen (e.g., Figs 2-3, col 4 lines 9-35), on the other hand and in a related field, shows a silicon nitride layer (e.g., 48) that is exposed to an oxygen plasma to transform that transforms most of the dangle bonds and Si-N bonds on the surface of the silicon nitride layer 48 into Si-O bonds or Si-ON bonds so that optical properties across the surfaces of the silicon nitride layer 48 are equalized. This reduces the possibility of resist lift off and improves patterning uniformity at subsequent lithography steps.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a oxygen plasma introduced to a passivation layer in the method of Yim/Burrell/Culverhouse, as taught by Chen, to improve adhesion of the passivation surface to a photoresist process (e.g., Col 2, lines 51-59).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over You et. al (CN 105575825 A, Hereinafter You-5825) in view of Yim/Burrell/Culverhouse.
Regarding Claim 11, You-5825 (e.g., Figs 2d-2j, Pages 5-9 of PDF provided) discloses a manufacturing method for a chip packaging structure, comprising:
providing a die (e.g., 111-113) and forming a plastic encapsulation layer encapsulating the die (e.g., first encapsulation layer 132, made of epoxy resin);
forming a through hole (e.g., Fig 2e), in which the copper layer (e.g., 120) is exposed, in the plastic encapsulation layer by laser drilling (e.g., “laser perforation openings are formed in the first encapsulation layer 132 to expose the surface of the conductive bump 120”;
forming a pin over the plastic encapsulation layer and the copper layer (e.g., Fig 2f, conductive bumps 134); and
forming the chip packaging structure by dicing (e.g., Fig 2i).
While You-5825 shows a die with copper pillars (e.g., 120), it is silent about a die formed with the method of claim 2. Yim/Burrell/Culverhouse (see claim 2 rejection), on the other hand and in a related field, teaches a die that has bumps formed with the method steps of claim 2 and includes a copper pillar bumping technique with superior adhesion to Al pads
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the die of Yim/Burrell/Culverhouse with the improved copper bumps in the method steps of You-5825 to include a die with an improved bumping technique.
Regarding Claim 12, You-5825 (e.g., Figs 2d-2j, Pages 5-9 of PDF provided) discloses the formed plastic encapsulation layer encapsulates a plurality of the dies (e.g., Fig 2h), and wherein the dicing is performed so that the chip packaging structure each comprises one of the dies (e.g., Fig 2i).
Regarding Claim 13, You-5825 (e.g., Figs 2d-2j, Pages 5-9 of PDF provided) wherein before the pin is formed, a rewiring layer (e.g., a rewiring layer 133) is formed over the plastic encapsulation layer and the copper layer, and wherein the pin is formed on the rewiring layer(e.g., Fig 2f/2g shows the rewiring layer 133 formed prior to the pins 134)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over You et. al in view of Yim/Burrell/Culverhouse further in view of Lin et al (US 20140091454 A1, Hereinafter Lin).
Regarding Claim 14, while You-5825 (e.g., Figs 2d-2j, Pages 5-9 of PDF provided) discloses a through hole to expose a copper layer, it is silent about a through hole has a bottom sized smaller than the copper layer, and wherein the bottom of the through hole is sized smaller than at a top of the through hole.
Lin (e.g., Fig 4d-4f [0063]-[0066]), on the other hand and in a related field of packaging, teaches a fan-out build-up interconnect structure or RDL (e.g., electrically conductive layer 186), formed on the surface of a top of a copper layer (e.g., 132) where a width of the end of the RDL contacting the copper layer is smaller than the width of the copper layer and where the profile of 186 is narrow nearer to the copper layer.
The prior art seems to teach an arrangement of top/bottom surface widths satisfying the limitation “through hole has a bottom sized smaller than the copper layer, and wherein the bottom of the through hole is sized smaller than at a top of the through hole.” Additionally, with regards to the particular ratio of surface dimensions claimed, it is also noted that the specification fails to provide teachings about the criticality of having tapered through hole shape and the courts have held that differences in shape will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed ratio between widths and since Lin teaches an arrangement of widths known in RDL formation, it would have been obvious to one of ordinary skill in the art to use these (width ratio values) in the device of You in view of Yim/Burrell/Culverhouse
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed dimensions ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions ratios or upon another variable recited in a claim, the applicant must show that the chosen ratios are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to the claims filed on 11/24/2025 have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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/ANEESA RIAZ BAIG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814