Prosecution Insights
Last updated: August 18, 2026
Application No. 18/020,758

SEMICONDUCTOR DEVICE

Final Rejection §102
Filed
Feb 10, 2023
Priority
Aug 27, 2020 — JP 2020-143470 +1 more
Examiner
TRAN, TRANG Q
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
592 granted / 730 resolved
+13.1% vs TC avg
Moderate +7% lift
Without
With
+7.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
41 currently pending
Career history
773
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.7%
+6.7% vs TC avg
§102
35.7%
-4.3% vs TC avg
§112
16.2%
-23.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 730 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 9-12 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2020/0212185, as disclosed in previous office action). As for claim 9, Yamazaki et al. disclose in Fig. 29 and the related text a semiconductor device comprising: a first device layer 290-1 to an n-th (n is a natural number of 2 or more) device layer 290-n which are stacked over a substrate in order (Fig. 29, [0006]), wherein each of the first device layer to the n-th device layer comprises an oxide semiconductor device 200, a first conductor 242a, and a second conductor 240a, wherein the first device layer comprises a first barrier insulating film 211 under the oxide semiconductor device (Fig. 29), wherein the n-th device layer comprises a second barrier insulating film 283/284/286/287 over the second conductor 240a, wherein the first barrier insulating film 211 and the second barrier insulating film 283/284/286/287 are configured to inhibit diffusion of hydrogen, wherein in each of the first device layer to the n-th device layer, the first conductor 242a is placed over the oxide semiconductor device 200 so as to be electrically connected to the oxide semiconductor device (Fig. 29), and the second conductor 240a is placed over the first conductor (Fig. 29), wherein an opening (where 21 is formed in) reaching the first barrier insulating film 211 in the first device layer is formed in the first device layer to the n-th device layer (Fig. 29), wherein the opening is provided so as to surround the oxide semiconductor device in the first device layer to the n-th device layer (Fig. 29), and wherein the second barrier insulating film 283/284/286/287 in the n-th device layer is provided to cover the oxide semiconductor device in the first device layer to the n-th device layer. The limitation “the first barrier insulating film to the third/second barrier insulating film are configured to inhibit diffusion of hydrogen” has not been given patentable weight because it is considered to be intended use and/or functional language. This type of description does not affect the structure of the final device. It is respectfully noted that intended use and/or other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 240a USPQ 430, 433 (CCPA 1977). As for claim 10, Yamazaki et al. disclose the semiconductor device according to claim 9, wherein the second barrier insulating film 283/284/286/287 in the n-th device layer is in (thermally/electrically) contact with the first barrier insulating film 211 in the first device layer in a region where the second barrier insulating film 283/284/286/287 in the n-th device layer does not overlap with the oxide semiconductor device in the first device layer to the n-th device layer (Fig. 29). As for claim 11, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the first barrier insulating film 211 and second barrier insulating film 283/284/286/287 are silicon nitride ([0166] and [0439]). As for claim 12, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the second barrier insulating film 283/284/286/287 comprises a first layer 283 and a second layer 284/286/287 over the first layer, and wherein the first layer has a lower hydrogen concentration than the second layer ([0162], [0170] and [0439]). Response to Arguments Applicant's response filed on 06/02/2026 is acknowledged and is answered as follows. Applicant’s arguments, see pgs 4-7, with respect to claim 9 rejection that “the second barrier insulating film in the n-th device layer is provided to cover the oxide semiconductor device in the first device layer to the n-th device layer” have been fully considered but they are not persuasive in view of the following reasons. Fig. 29 of Yamazaki et al. teach the second barrier insulating film 283/284/286/287 in the n-th device layer 290_n is provided to cover the oxide semiconductor device 200 in the first device layer to the n-th device layer. Therefore, Yamazaki et al. still disclosed the claimed invention. In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Feb 10, 2023
Application Filed
Mar 04, 2026
Non-Final Rejection mailed — §102
Jun 02, 2026
Response Filed
Jun 25, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
88%
With Interview (+7.0%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 730 resolved cases by this examiner. Grant probability derived from career allowance rate.

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