Prosecution Insights
Last updated: April 19, 2026
Application No. 18/020,758

SEMICONDUCTOR DEVICE

Non-Final OA §102§112
Filed
Feb 10, 2023
Examiner
TRAN, TRANG Q
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co. Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
88%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
579 granted / 716 resolved
+12.9% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
34 currently pending
Career history
750
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.3%
+5.3% vs TC avg
§102
36.1%
-3.9% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 716 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/17/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1, 3, 9 are failing to particularly point out and distinctly define the metes and bounds of the subject matter because it is unclear what is the preamble of the claim. Claim 3 line 16 recites the limitation of “an opening” is unclear. Is that the same or different from an opening as previously claimed? Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-18 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2020/0212185). As for claims 1, 3 and 9, Yamazaki et al. disclose in Fig. 29 and the related text a semiconductor device comprising a first device layer 290-1 to an n-th (n is a natural number of 2 or more) device layer 290-n which are stacked over a substrate in order (Fig. 29, [0006]), wherein each of the first device layer to the n-th device layer comprises a first barrier insulating film 211, a second barrier insulating film 272/273/280/287, a third barrier insulating film 298/214, an oxide semiconductor device 290, a first conductor 240a, and a second conductor 246a, and wherein in each of the first device layer 290-1 to the n-th device layer, the oxide semiconductor device 290-1 is placed over the first barrier insulating film 211 (Fig. 29), the second barrier insulating film 280 is placed to cover the oxide semiconductor device (fig. 29) or the second barrier insulating film 298/287 over the second conductor, the first conductor 240a is placed so as to be electrically connected to the oxide semiconductor device through an opening formed in the second barrier insulating film (Fig. 29), the second conductor 246a is placed over the first conductor (Fig. 29), the third barrier insulating film 298 is placed over the second conductor and the second barrier insulating film (fig. 29), and wherein the first barrier insulating film to the third/second barrier insulating film are configured to inhibit diffusion of hydrogen (Yamazaki et al. teach the first barrier insulating film to the third/second barrier insulating film having the same material (as seen in claim 5 below) as claimed invention, therefore it is capable to configured to inhibit diffusion of hydrogen, also see [0115] and [0166]) wherein an opening (opening where 283/284 is formed) reaching the first barrier insulating film 211 in the first device layer is formed in the first device layer to the n-th device layer (Fig. 29), wherein the opening is provided so as to surround the oxide semiconductor devices 290-1 in the first device layer to the n-th device layer 290-n, and wherein the second barrier insulating film 272/273/280/287 in the n-th device layer is provided to cover the oxide semiconductor devices in the first device layer to the n-th device layer (Fig. 29). The limitation “the first barrier insulating film to the third/second barrier insulating film are configured to inhibit diffusion of hydrogen” has not been given patentable weight because it is considered to be intended use and/or functional language. This type of description does not affect the structure of the final device. It is respectfully noted that intended use and/or other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). As for claim 2, Yamazaki et al. disclose the semiconductor device according to claim 1, wherein the second barrier insulating film 280/287 is in contact with the first barrier insulating film in a region where the second barrier insulating film does not overlap with the oxide semiconductor device (Fig. 29). As for claims 4 and 10, Yamazaki et al. disclose the semiconductor device according to claim 3, wherein the second barrier insulating film 280/287 or 298/287 in the n-th device layer is in contact with the first barrier insulating film 211 in the first device layer in a region where the second barrier insulating film in the n-th device layer does not overlap with the oxide semiconductor device in the first device layer to the n-th device layer (Fig. 29). As for claims 5 and 11, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the first barrier insulating film 211 to the third barrier insulating film 298 are silicon nitride ([0166], [0141] and [0439]). As for claims 6 and 12, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the third barrier insulating film 298/214 comprises a first layer 298 and a second layer 214 over the first layer, and wherein the first layer has a lower hydrogen concentration than the second layer ([0162], [0318] and [0439]). As for claims 7-8 and 13-14, Yamazaki et al. disclose the semiconductor device according to claim 6/9, wherein the first layer is an insulating film formed by a sputtering method; and wherein the second layer is an insulating film formed by a PEALD method. The recited limitation “formed by a sputtering method” and “formed by a PEALD method” are drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113. As for claim 15, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the first conductor 240a is placed so as to be embedded in an interlayer insulating film 280 formed over the oxide semiconductor device (Fig. 29). As for claim 16, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the substrate is a silicon substrate [0006]. As for claim 17, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein a transistor is formed on the substrate [0006]. As for claim 18, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the oxide semiconductor film 230 included in the oxide semiconductor device 290 comprises one or more of In, Ga, and Zn [0192]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Feb 10, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604504
Shielding Structure for Silicon Carbide Devices
2y 5m to grant Granted Apr 14, 2026
Patent 12593684
SEMICONDUCTOR PACKAGE INCLUDING HEAT DISSIPATION STRUCTURE
2y 5m to grant Granted Mar 31, 2026
Patent 12593699
PACKAGE STRUCTURE
2y 5m to grant Granted Mar 31, 2026
Patent 12581929
Semiconductor Devices and Methods for Forming a Semiconductor Device
2y 5m to grant Granted Mar 17, 2026
Patent 12557672
ELECTRONIC DEVICE HAVING SUBSTRATE
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
88%
With Interview (+7.4%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 716 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month