Prosecution Insights
Last updated: October 04, 2026
Application No. 18/020,758

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Feb 10, 2023
Priority
Aug 27, 2020 — JP 2020-143470 +1 more
Examiner
TRAN, TRANG Q
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
3 (Non-Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
600 granted / 738 resolved
+13.3% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
47 currently pending
Career history
776
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.1%
+7.1% vs TC avg
§102
35.5%
-4.5% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 9-12 and 19 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2020/0212185, as disclosed in previous office action). As for claim 9, Yamazaki et al. disclose in Fig. 29 and the related text a semiconductor device comprising: a first device layer 290-1 to an n-th (n is a natural number of 2 or more) device layer 290-n which are stacked over a substrate in order (Fig. 29, [0006]), wherein each of the first device layer 290-1 to the n-th device layer comprises a structure body comprising an oxide semiconductor device 230/242a/243a/250/260 and a first conductor 240a, and a second conductor 240a, wherein the first device layer comprises a first barrier insulating film 211 under the oxide semiconductor device (Fig. 29), wherein the n-th device layer comprises a second barrier insulating film 283/284/286/287 over and in (thermally) contact with the second conductor 246a of the n-th device layer (Fig. 29), wherein in each of the first device layer to the n-th device layer, the first conductor 240a is placed over the oxide semiconductor device so as to be electrically connected to the oxide semiconductor device (Fig. 29), and the second conductor 246a is placed over the first conductor (Fig. 29), wherein an opening (where 21 is formed in) reaching the first barrier insulating film 211 in the first device layer is formed in the first device layer to the n-th device layer (Fig. 29), wherein the opening is provided so as to surround the oxide semiconductor device in the first device layer to the n-th device layer (Fig. 29), and wherein the second barrier insulating film 283/284/286/287 is in (thermally) contact with a side surface of the structure body in the first device layer to side surface of the structure body in the n-th device layer (fig. 29). As for claim 10, Yamazaki et al. disclose the semiconductor device according to claim 9, wherein the second barrier insulating film 283/284/286/287 in the n-th device layer is in (thermally/electrically) contact with the first barrier insulating film 211 in the first device layer in a region where the second barrier insulating film 283/284/286/287 in the n-th device layer does not overlap with the oxide semiconductor device in the first device layer to the n-th device layer (Fig. 29). As for claim 11, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the first barrier insulating film 211 and second barrier insulating film 283/284/286/287 are silicon nitride ([0166] and [0439]). As for claim 12, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the second barrier insulating film 283/284/286/287 comprises a first layer 283 and a second layer 284/286/287 over the first layer, and wherein the first layer has a lower hydrogen concentration than the second layer ([0162], [0170] and [0439]). As for claim 19, Yamazaki et al. disclose the semiconductor device according to any one of claim 1, wherein the second barrier insulating film 283/284/286/287 comprises a first layer 283/284/287 and a second layer 286 over the first layer, and wherein a thickness of the second layer is smaller than a thickness of the first layer (Fig. 29). Response to Arguments Applicant's response filed on 06/02/2026 is acknowledged and is answered as follows. Applicant’s arguments, see pgs 4-6, with respect to claim 9 rejection that “the n-th device layer comprises a second barrier insulating film over and in contact with the second conductor of the n-th device layer” have been fully considered but they are not persuasive in view of the following reasons. Fig. 29 of Yamazaki et al. teach the n-th device layer 290_1/290_n comprises a second barrier insulating film 283/284/286/287 over and in (thermally) contact with the second conductor 246a of the n-th device layer. Therefore, Yamazaki et al. still disclosed the claimed invention. In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Feb 10, 2023
Application Filed
Mar 04, 2026
Non-Final Rejection mailed — §102
Jun 02, 2026
Response Filed
Jun 25, 2026
Final Rejection mailed — §102
Sep 04, 2026
Request for Continued Examination
Sep 08, 2026
Response after Non-Final Action
Sep 17, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
89%
With Interview (+7.3%)
2y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allowance rate.

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