DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Receipt is acknowledged of the preliminary amendment, filed March 17, 2023, which has been entered. Claims 1-20 are pending.
Claim Objections
Claims 10 and 16 are objected to because of the following informalities: “the ferroelectric material” (see claim 10, line 3 and claim 16, line 2) lacks proper antecedent basis. Either “the” should be replaced with --a--, or claims 10 and 16 should depend from claims 9 and 15, respectively. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 and 6-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al (US 2013/0257379 A1) in view of Lin et al (US 2020/0286695 A1).
Regarding claim 1, Kato et al teaches (see Figs. 1, 2 & 4): A control circuit (10) comprising a first resistance circuit (28 & 29), a second resistance circuit (30 & 31), a comparator (201), and a memory circuit (103), wherein the comparator comprises a first input terminal (the + input terminal), a second input terminal (the – input terminal), and a first output terminal (see the output terminal of 201, shown in Fig. 2) outputting a comparison result of the first input terminal and the second input terminal, wherein one terminal of the first resistance circuit is electrically connected to a positive electrode of a secondary battery (the terminal of 28 connected to a positive terminal Vcc of secondary battery 11), wherein the other terminal (for example, the terminal between 28 & 29 connected at n1) of the first resistance circuit is electrically connected to the first input terminal (the + terminal of 201) and one terminal of the second resistance circuit (the terminal at n1 is connected to a terminal GND1 of the second resistance circuit through 29), wherein the memory circuit is configured to retain first data (trimming data, see Fig. 4 and para. 0020), wherein the control circuit is configured to generate a first signal (via trimming circuit 455) and a second signal (via trimming circuit 456) by using the first data, to adjust resistance (variable resistance 29 is adjusted) of the first resistance circuit by supplying the first signal to the first resistance circuit, to adjust resistance of the second resistance circuit (variable resistance 31 is adjusted) by supplying the second signal to the second resistance circuit (see para. 0048), and to stop one of charging and discharging of the secondary battery in accordance with output from the first output terminal (see paras. 0049, 0050 & 0055).
Kato et al does not specifically teach wherein the memory circuit comprises a capacitor comprising a ferroelectric layer.
Lin et al teaches (see Figs. 1, 3 & 5) a memory circuit that comprises a capacitor (COB) comprising a ferroelectric layer (ferroelectric material 103 or 303) (also see paras. 0039, 0042, 0046-0051).
In view of Lin et al’s teachings, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to modify Kato et al to include wherein the memory circuit comprises a capacitor comprising a ferroelectric layer, in order to utilize an improved memory with longer retention and high charge density (see the abstract and paras. 0001 & 0019-0021, of Lin et al).
Regarding claim 2, Kato et al as modified by Lin et al teaches: the control circuit according to claim 1 (see above).
Kato et al does not specifically teach how variable resistance (29) is adjusted, and thus, does not teach: wherein the first resistance circuit comprises a plurality of pairs of one resistor and one switch, wherein the one switch of the pair of the one resistor and the one switch is configured to change a current flowing in the one resistor, and wherein the control circuit is configured to control, by using the first signal, operation of the switch of each of the plurality of pairs.
However, Kato et al does teach a variable resistance circuit (see Fig. 3) used to provide a voltage reference, wherein the first resistance circuit comprises a plurality of pairs of one resistor and one switch (R1 & 301; R2 & 302; … R6 & 306), wherein the one switch of the pair of the one resistor and the one switch is configured to change a current flowing in the one resistor (current through the resistors is changed by opening/closing of the switches), and wherein a control circuit (trimming circuits) is configured to control, by using a first signal (trimming signal), operation of the switch of each of the plurality of pairs (see para. 0054).
Therefore, in view of Kato et al’s teachings in Fig. 3, it would have been obvious to one of ordinary skill in the art prior to the effective filing date, to utilize as the variable resistance 29 of Kato et al as modified by Lin et al, wherein the first resistance circuit comprises a plurality of pairs of one resistor and one switch, wherein the one switch of the pair of the one resistor and the one switch is configured to change a current flowing in the one resistor, and wherein the control circuit is configured to control, by using the first signal, operation of the switch of each of the plurality of pairs, since this is a known circuit for adjusting a resistance value and voltage reference value.
Regarding claim 3, Kato et al as modified by Lin et al teaches: The control circuit according to claim 1, wherein the second input terminal (the – terminal of 201) is supplied with a signal (Vref1) corresponding to an upper limit of a charging voltage or a signal corresponding to a lower limit of a discharging voltage (since CMP1 of 201 detects an overvoltage, see para. 0050 of Kato et al, Vref1 can be considered an upper limit of a charging voltage).
Regarding claim 13, Kato et al as modified by Lin et al teaches: an electronic device (battery pack 1) comprising: the control circuit (10) according to claim 1; and a secondary battery (11) (see Figs. 1 & 2 of Kato et al).
Regarding claim 6, Kato et al teaches (see Figs. 1, 2, & 4): A control circuit (10) comprising: a first terminal (VCC and/or VIN) electrically connected to a positive electrode of a secondary battery (11); a second terminal (GND) electrically connected to a negative electrode of the secondary battery (11); a third terminal (see output terminals of transistor control circuit 110) electrically connected to a gate of a power transistor (13 and/or 14) controlling electrical connection between the secondary battery and a charger or a load (a charger or load connected to T1 and T4); a detection portion (117) electrically connected to the first terminal and the second terminal (see Fig. 1); a control portion (108, comprising 112 & 113) electrically connected to the detection portion; and a memory circuit (103) electrically connected to the control portion, wherein the detection portion comprises a resistance circuit (28 & 29 and 30 & 31) whose resistance has been adjusted (via a trimming circuit) in accordance with data (trimming data) stored in the memory circuit (103), and wherein the control portion is configured to determine that the secondary battery (11) is overdischarged in accordance with a result of comparing (via CMP3 of 203) a reference potential (the potential at n2) input from the detection portion (117) and a potential (Vref3) of the first terminal (via reference voltage generation part 23) or a potential of the second terminal, and to output a signal (the output signal(s) of 110) with which the power transistor (13 and/or 14) is brought into an off state to the third terminal (see output terminals of transistor control circuit 110) when the secondary battery is determined to be overdischarged (see paras. 0049, 0050 & 0055).
Kato et al does not specifically teach wherein the memory circuit comprises a memory cell comprising a ferroelectric layer between a pair of electrodes, a transistor electrically connected to the memory cell.
Lin et al teaches (see Figs. 1, 3 & 5) a memory circuit that comprises a memory cell (see Fig. 5) comprising a ferroelectric layer (ferroelectric material 103 or 303) between a pair of electrodes (metal layers 101 or 301 and 102 or 302), a transistor (M1 and/or 500) electrically connected to the memory cell (also see paras. 0039, 0042, 0046-0051).
In view of Lin et al’s teachings, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to modify Kato et al to include wherein the memory circuit comprises a memory cell comprising a ferroelectric layer between a pair of electrodes, a transistor electrically connected to the memory cell, in order to utilize an improved memory with longer retention and high charge density (see the abstract and paras. 0001 & 0019-0021, of Lin et al).
Kato et al as modified by Lin et al does not specifically teach that the memory circuit includes a decoder to which a signal from the memory cell is output (Note: para. 0124 of applicant’s specification refers to SR-MUX in Fig. 4B as a decoder that has a function of sequentially outputting memory data).
However, it was old and well known to those of ordinary skill in the art prior to the effective filing date to use a multiplexer (MUX) with a memory circuit to route data from the memory cells to the output of the memory circuit.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to include, with the memory circuit of Kato et al as modified by Lin et al, wherein the memory circuit includes a decoder to which a signal from the memory cell is output, since this is a common memory circuit component to provide memory cell data onto the output line of a memory cell.
Regarding claim 7, Kato et al teaches (see Figs. 1, 2, & 4): A control circuit (10) comprising: a first terminal (VCC and/or VIN) electrically connected to a positive electrode of a secondary battery (11); a second terminal (GND) electrically connected to a negative electrode of the secondary battery (11); a third terminal (see output terminals of transistor control circuit 110) electrically connected to a gate of a power transistor (13 and/or 14) controlling electrical connection between the secondary battery and a charger or a load (a charger or load connected to T1 and T4); a detection portion (117) electrically connected to the first terminal and the second terminal (see Fig. 1); a control portion (108, comprising 112 & 113) electrically connected to the detection portion; and a memory circuit (103) electrically connected to the control portion, wherein the detection portion comprises a resistance circuit (28 & 29 and 30 & 31) whose resistance has been adjusted (via a trimming circuit) in accordance with data (trimming data) stored in the memory circuit (103), and wherein the control portion is configured to determine that the secondary battery (11) is overcharged in accordance with a result of comparing (via CMP1 of 201) a reference potential (the potential at n1) input from the detection portion (117) and a potential (Vref1) of the first terminal (via reference voltage generation part 21) or a potential of the second terminal, and to output a signal (the output signal(s) of 110) with which the power transistor (13 and/or 14) is brought into an off state to the third terminal (see output terminals of transistor control circuit 110) when the secondary battery is determined to be overcharged (see paras. 0049, 0050 & 0055).
Kato et al does not specifically teach wherein the memory circuit comprises a memory cell comprising a ferroelectric layer between a pair of electrodes, a transistor electrically connected to the memory cell.
Lin et al teaches (see Figs. 1, 3 & 5) a memory circuit that comprises a memory cell (see Fig. 5) comprising a ferroelectric layer (ferroelectric material 103 or 303) between a pair of electrodes (metal layers 101 or 301 and 102 or 302), a transistor (M1 and/or 500) electrically connected to the memory cell (also see paras. 0039, 0042, 0046-0051).
In view of Lin et al’s teachings, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to modify Kato et al to include wherein the memory circuit comprises a memory cell comprising a ferroelectric layer between a pair of electrodes, a transistor electrically connected to the memory cell, in order to utilize an improved memory with longer retention and high charge density (see the abstract and paras. 0001 & 0019-0021, of Lin et al).
Kato et al as modified by Lin et al does not specifically teach that the memory circuit includes a decoder to which a signal from the memory cell is output (Note: para. 0124 of applicant’s specification refers to SR-MUX in Fig. 4B as a decoder that has a function of sequentially outputting memory data).
However, it was old and well known to those of ordinary skill in the art prior to the effective filing date to use a multiplexer (MUX) with a memory circuit to route data from the memory cells to the output of the memory circuit.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to include, with the memory circuit of Kato et al as modified by Lin et al, wherein the memory circuit includes a decoder to which a signal from the memory cell is output, since this is a common memory circuit component to provide memory cell data onto the output line of a memory cell.
Regarding claims 8 and 14, Kato et al as modified by Lin et al teaches: The control circuit according to claims 6 and 7, respectively, wherein the control circuit (10) comprises a fourth terminal (T2, Fig. 1) to which a signal from the outside is input (see para. 0031).
Kato et al as modified by Lin et al does not specifically teach wherein the data is written to the memory circuit by supply of a signal from outside of the control circuit.
However, it was old and well known to those of ordinary skill in the art prior to the effective filing date to write data to a memory circuit by supply of a signal from outside of the circuit.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to include, with the memory circuit of Kato et al as modified by Lin et al, wherein the data is written to the memory circuit by supply of a signal from outside of the control circuit, since this would allow for a manufacturer to write the data to the memory circuit during manufacture and/or provide updates to the data stored in the memory circuit.
Regarding claims 9 and 15, Kato et al as modified by Lin et al teaches: The control circuit according to claims 6 and 7, respectively, wherein a ferroelectric material of the ferroelectric layer of the memory circuit comprises an oxide comprising hafnium and zirconium (see paras. 0019, 0041, 0043, 0044 and 0053 of Lin et al).
Regarding claims 10 and 16, Kato et al as modified by Lin et al teaches: The control circuit according to claims 6 and 7, respectively, wherein the ferroelectric material of the ferroelectric layer has an orthorhombic crystal structure (see paras. 0019, 0041 and 0044 of Lin et al).
Regarding claims 11 and 17, Kato et al as modified by Lin et al teaches: The control circuit according to claims 6 and 7, respectively, wherein the pair of electrodes of the memory circuit comprise titanium nitride (see paras. 0053-0055 of Lin et al).
Regarding claims 12 and 18, Kato et al as modified by Lin et al teaches: The control circuit according to claims 6 and 7, respectively, wherein the transistor is a Si transistor (see paras. 0053-0055 of Lin et al).
Regarding claims 19 and 20, Kato et al as modified by Lin et al teaches: An electronic device (battery pack 1) comprising: the control circuit (10) according to claims 6 and 7, respectively; and a secondary battery (11) (see Figs. 1 and 2 of Kato et al).
Allowable Subject Matter
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, Kato et al and Lin et al do not teach: the control circuit according to claim 1, further comprising a third resistance circuit and a second comparator, wherein the second comparator comprises a third input terminal, a fourth input terminal, and a second output terminal outputting a comparison result of the third input terminal and the fourth input terminal, wherein the other terminal of the second resistance circuit is electrically connected to the third input terminal and one terminal of the third resistance circuit, wherein the other terminal of the third resistance circuit is electrically connected to a negative electrode of the secondary battery, and wherein the control circuit is configured to generate a third signal by using the first data, to adjust resistance of the third resistance circuit by supplying the third signal to the third resistance circuit.
Furthermore, without the benefit of applicant’s teachings, one of ordinary skill in the art prior to the effective filing date would not have been motivated to modify the control circuit as taught by Kato et al as modified by Lin et al to include the additional circuit components and connections as recited in claim 4.
Claim 5 depends from claim 4 and would be allowable for at least the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see the additional references cited on the attached PTO-892, which are directed to battery control circuits or ferroelectric memory circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Fureman whose telephone number is (571)272-2391. The examiner can normally be reached M-F 8:30 am - 5:00 pm.
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/JARED FUREMAN/Primary Examiner, Art Unit 2859