DETAILED ACTION
This Office Action is in response to the Election filed on August 22, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A, alleged claims 1-14 in the reply filed on August 22, 2025 is acknowledged. The traversal is on the ground(s) that the species are improperly defined. This is not found persuasive. The applicant’s arguments state that
“independent claim 1 recites two (i.e., first and second) memory cells (e.g., MC) and the two memory cells are connected via a switch (e.g., SW), as shown in Figs. 2, 3 and 7A. Independent claim 8 is also supported by at least Figs. 2-4. In this regard, it is noted that claim 8 recites a first driver circuit (e.g., any of WBD, RWD, RBD, WWD shown in Figs. 2-3) and (one) memory cell (e.g., MC).”
Although the examiner’s restriction has some improperly defined elements, the applicant’s argument present separate and distinct species for species A and B.
Species A Figs. 2, 3, 7A
-two (i.e., first and second) memory cells (e.g., MC) and
the two memory cells are connected via a switch (e.g., SW).
Claims 1-7
Species B Figs. 2-4
-a first driver circuit (e.g., any of WBD, RWD, RBD, WWD shown in Figs. 2-3) and
(one) memory cell (e.g., MC).
Claims 8-14
After further consideration, it is agreed that these elements best represent the species previous defined as species A, B, C. The requirement is still deemed proper and is therefore made FINAL. The applicant elected species A with traverse and species A includes claims 1-7.
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Rakshit et al. (US Pub. 2019/0318775 A1) in view of Ishizu et al. (US Pub. 2020/0211628 A1).
In re claim 1, Rakshit et al. shows (figs. 1A, 1B, 2) a semiconductor device comprising a first memory cell , and a second memory cell, wherein the first memory cell (100) comprises a first transistor (120), a second transistor (110), and a first capacitor (114), wherein the second memory cell (another 100 below the first memory cell) comprises a third transistor (another 120 below the first memory cell), a fourth transistor (another 110 below the first memory cell), and a second capacitor (another 114 below the first memory cell), wherein the first capacitor and the second capacitor each comprise a ferroelectric layer [0015] between a pair of electrodes, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, wherein the gate of the second transistor is electrically connected to one of the pair of electrodes of the first capacitor, wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, wherein the gate of the fourth transistor is electrically connected to one of the pair of electrodes of the second capacitor (the same as in the first memory cell), and wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor. Rakshit shows all of the elements of the claims except wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor via the switch. The limitation in question is not distinguishable over the cited art since it is well known in the art to use to use switches to selectively connect device components. Ishizu et al. shows (fig. 10) a circuit diagram in which components are connected via a switch. With this configuration, the circuit components can be selectively connected. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the memory cell of Rakshit by using a switch as taught by Ishizu to selectively connect the device components.
In re claims 2-7, Rakshit combined with Ishizu show all of the elements of the claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. You (US Pub. 2021/0028178 A1), Aoki (US Pub. 2023/0326491 A1), Matsuzaki (US 9,773,787 B2), and Morris (KR-20180013861 A) also disclose various elements of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815