Prosecution Insights
Last updated: October 02, 2026
Application No. 18/035,150

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE

Non-Final OA §102§103§112
Filed
May 03, 2023
Priority
Nov 17, 2020 — JP 2020-191029 +1 more
Examiner
KIM, JAY C
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
3 (Non-Final)
49%
Grant Probability
Moderate
3-4
OA Rounds
1m
Est. Remaining
71%
With Interview

Examiner Intelligence

Grants 49% of resolved cases
49%
Career Allowance Rate
430 granted / 872 resolved
-18.7% vs TC avg
Strong +22% interview lift
Without
With
+21.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
62 currently pending
Career history
929
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
40.8%
+0.8% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
43.7%
+3.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 872 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office Action is in response to RCE filed June 17, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is not clear what “a U-shape” recited on line 2 refers to, because even though Applicants originally disclosed in paragraph [0085] of current application that “In the cross-sectional view, the conductive layer 112b has a U-shape when being provided in the groove 111”, the actual shape of the conductive layer 112b shown in Fig. 9 of current application, which is directed to Applicants’ elected species, does not exactly have “a U-shape” since (i) the phrase “a U-shape” of a structural element in semiconductor industry has commonly been used to describe a shape that is symmetrical along a vertical center line of the structural element, (ii) however, the conductive layer 112b in Fig. 9 of current application is not symmetrical since the left side of the conductive layer 112b is of a corrugated or irregular shape, while the right side of the conductive layer 112b is of a planar shape, (iii) therefore, it is not clear whether Applicants’ claimed “U-shape” implies an asymmetrical shape or can be a symmetrical “U-shape”, and (iv) if it is the former, it is not clear to what degree the “U-shape” can be asymmetrical, and if it is the latter, it is not clear how a symmetrical “U-shape” can be achieved since the underlying layers for the conductive layer 112b may not be conducive to achieving a symmetrical “U-shape” of the conductive layer 112b. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Manfrini (US 11,398,597) Regarding claim 1, Manfrini discloses a semiconductor device (Fig. 6E) comprising: a substrate (5156), because (a) Applicants do not specifically claim what “a substrate” is formed of, (b) Merriam-Webster dictionary defines “substrate” as “an underlying support”, and (c) therefore, the conductive patterns 5156 can be referred to as “a substrate” since the conductive patterns 5156 support a structure formed on top of them; an insulating layer (5182 in Fig. 6C) (col. 20, line 6) over the substrate; and a transistor (one of T60’s shown in Fig. 6E) (col. 20, line 58) over the substrate (5156) and the insulating layer, wherein the insulating layer (5182) has a groove (one of grooves shown in Fig. 6C), wherein the transistor comprises a gate electrode (5250) (col. 20, line 56), a gate insulating layer (5240) (col. 20, lines 55-56), a semiconductor layer (5230) (col. 20, line 55 and Abstract where Manfrini states that “The channel strip includes a semiconductor oxide material.”), and a pair of conductive layers (5170 and 5190) (col. 20, lines 34-35), wherein one of the pair of the conductive layers (5190) comprises a region overlapping with the insulating layer, see Fig. 6C, wherein the other of the pair of the conductive layers (5170) comprises a region not overlapping with the insulating layer, see Fig. 6C where portions of the source contacts 5170 are exposed, wherein a level of an end surface of the other of the pair of the conductive layers is lower than a level of an end surface of the one of the pair of the conductive layers, wherein each of the pair of the conductive layers is in electrical contact with the semiconductor layer, wherein the semiconductor layer (5230) comprises a region overlapping with the gate electrode (5250) through the gate insulating layer (5240), wherein the gate electrode is in contact with a top surface and a side surface of the insulating layer, see the illustration below where the gate electrode 5250 contacts an edge of the top surface of the insulating layer 5182 labeled “top” and a side surface of the insulating layer 5182 labeled “side”, because Applicants do not specifically claim how the gate electrode is in contact with the top surface of the insulating layer, and wherein a part of the gate electrode (5250) and a part of the semiconductor layer are in the groove. PNG media_image1.png 452 786 media_image1.png Greyscale Regarding claims 2 and 11, Manfrini further discloses that each of the pair of the conductive layers (5170 and 5190) is in electrical contact with a top surface of the semiconductor layer (5230), because charge carriers such as electrons and holes can move between each of the pair of the conductive layers 5170/5190 and the top surface of the semiconductor layer 5230 (claim 2), and ends of the other of the pair of the conductive layers (5170) extend along sides of the groove (claim 11). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Manfrini (US 11,398,597) The teachings of Manfrini are discussed above. Manfrini differs from the claimed invention by not showing that a taper angle of the insulating layer is greater than or equal to 45° and less than 90°. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a taper angle of the insulating layer can be greater than or equal to 45° and less than 90°, because (a) Applicants do not specifically claim how “a taper angle” is measured, i.e. which two lines or two planes are used to measure the claimed taper angle of the insulating layer, (b) in addition, the claimed range of “less than 90o” includes an angle substantially identical to 90o such as 89o or 89.9o, which can be obtained when the groove shown in Fig. 6C of Manfrini is not perfectly etched by a wet etching or a dry etching process, which has been commonly observed due to an imperfectness of a wet etching or a dry etching process, and (c) furthermore, at an atomic scale, the claimed taper angle of the insulating layer can be obtained when two atoms along an imaginary vertical line of Manfrini are etched slightly differently, and thus while one angle for one atom along the imaginary vertical line may be 90°, another angle for another atom along the imaginary vertical line may be slightly less than 90° that is within the claimed range, which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention since a wet etching or a dry etching process may not result in a perfectly vertical side surface with zero surface roughness. Allowable Subject Matter Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fu (US 11,127,768) Kim et al. (US 9,117,708) Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /J. K./Primary Examiner, Art Unit 2815 September 15, 2026
Read full office action

Prosecution Timeline

May 03, 2023
Application Filed
Oct 21, 2025
Non-Final Rejection mailed — §102, §103, §112
Jan 20, 2026
Response Filed
Mar 19, 2026
Final Rejection mailed — §102, §103, §112
Jun 17, 2026
Request for Continued Examination
Jun 22, 2026
Response after Non-Final Action
Sep 16, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751014
SEMICONDUCTOR DEVICE
2y 6m to grant Granted Sep 29, 2026
Patent 12727185
HEMT TRANSISTOR OF THE NORMALLY OFF TYPE INCLUDING A TRENCH CONTAINING A GATE REGION AND FORMING AT LEAST ONE STEP, AND CORRESPONDING MANUFACTURING METHOD
2y 9m to grant Granted Sep 01, 2026
Patent 12720889
IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS
2y 8m to grant Granted Aug 25, 2026
Patent 12707762
METHODS AND DEVICES FOR SOLID STATE NANOWIRE DEVICES
3y 10m to grant Granted Aug 11, 2026
Patent 12696697
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 7m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
49%
Grant Probability
71%
With Interview (+21.6%)
3y 6m (~1m remaining)
Median Time to Grant
High
PTA Risk
Based on 872 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month