DETAILED ACTION
This Office Action is in response to Amendment filed January 20, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 7 is objected to because of the following informalities: “the gate insulating side” should be replaced with “a gate insulating side”, because (a) Applicants do not claim “a gate insulating side” before claiming “the gate insulating side”, and (b) therefore, when strictly interpreted, the limitation “the gate insulating side” lacks the antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Lee et al. (US 2017/0317110)
Regarding claims 1 and 2, Lee et al. disclose a semiconductor device (Fig. 3) comprising: a substrate (500) ([0106]); an insulating layer (PT) ([0106] and [0116]) over the substrate; and a transistor (device structure in Fig. 3) over the substrate (500) and the insulating layer, wherein the insulating layer (PT) has an island shape, wherein the transistor comprises a gate electrode (GE) ([0106]), a gate insulating layer (GI) ([0121]), a semiconductor layer (700) ([0127]), and a pair of conductive layers (SE and DE), wherein one of the pair of the conductive layers (SE) comprises a region overlapping with the insulating layer, wherein the other of the pair of the conductive layers (DE) comprises a region not overlapping with the insulating layer, wherein a level of an end surface of the other of the pair of the conductive layers is lower than a level of an end surface of the one of the pair of the conductive layers, wherein each of the pair of the conductive layers (SE and DE) is in contact with the semiconductor layer, wherein the semiconductor layer (700) comprises a region overlapping with the gate electrode (GE) through the gate insulating layer (GI), and wherein the gate electrode is in contact with a top surface and a side surface of the insulating layer (claim 1), wherein each of the pair of the conductive layers (SE and DE) is in contact with a top surface of the semiconductor layer (700) (claim 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20170317110) The teachings of Lee et al. are discussed above.
Regarding claim 6, Lee et al. differ from the claimed invention by not showing that a taper angle of the insulating layer is greater than or equal to 45° and less than 90°.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a taper angle of the insulating layer PT of Lee et al. can be greater than or equal to 45° and less than 90°, because (a) the insulating layer PT shown in Fig. 3 of Lee et al. appears to have a taper angle in the claimed range, and therefore, when the semiconductor device shown in Fig. 3 of Lee et al. is manufactured to the scale, the claim limitation would be satisfied, and (b) the taper angle of the insulating layer PT should be controlled and optimized since the taper angle would control numerous device parameters such as a threshold voltage, a conductivity and a current flow through the semiconductor channel layer, etc.
Regarding claim 7, Lee et al. further disclose for the semiconductor device according to claim 1 that the semiconductor layer (700) comprises a first layer (one of sublayers of 700) and a second layer (another or the other of sublayers of 700) in this order from the gate insulating layer side, because (a) Lee et al. disclose that “For example, the semiconductor member 700, which is made of an oxide semiconductor, may contain at least one of ZnO, ZnGaO, ZnInO, ZnSnO, GaInZnO, CdO, InO, GaO, SnO, AgO, CuO, GeO, GdO, HfO, TiZnO, InGaZnO, and InTiZnO (emphasis added)” in paragraph [0127], and (b) therefore, Lee et al. at least implicitly disclose that “the semiconductor member 700 … may contain” two or more layers of “ZnO, ZnGaO, ZnInO, ZnSnO, GaInZnO, CdO, InO, GaO, SnO, AgO, CuO, GeO, GdO, HfO, TiZnO, InGaZnO, and InTiZnO”.
Lee et al. differ from the claimed invention by not showing that the second layer comprises a region with a crystallinity higher than a crystallinity of the first layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second layer can comprise a region with a crystallinity higher than a crystallinity of the first layer, because (a) the not-shown second layer can be in direct contact with the source electrode SE and the drain electrode DE, and therefore, the crystallinity of the second layer is more critical to the performance of the semiconductor device in comparison to the crystallinity of the first layer, (b) when the second layer is in direct contact with the source electrode SE and the drain electrode DE, and when the source and drain electrode are annealed together with the semiconductor layer to improve ohmic contact, which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, the second layer can comprise a region with a crystallinity higher than a crystallinity of the first layer during the formation of the improved ohmic contact since the thermal energy transferred to the second layer during the annealing process would rearrange atoms constituting the second layer to have a higher crystallinity.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicants' amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 March 16, 2026