DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments and the accompanying arguments, filed 01/08/2026, with respect to the amendments to claim 1 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Guo et al. (US 2021/0013242) and additional teachings of Izumi et al. (US 2003/0038306).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 2017/0329162) in view of Guo et al. (US 2021/0013242), Kajiyama (US 2018/0138260), Sasaki et al. (US 2018/0090515), and Izumi et al. (US 2003/0038306).
In reference to claim 1, Yamazaki et al. (US 2017/0329162), hereafter “Yamazaki,” discloses a semiconductor device, with reference to Figure 4B, comprising
a first wiring 21 over a substrate 29, paragraph 69,
a first resin layer 25 over the first wiring, paragraphs 119-121;
a first insulating layer 31 over the first resin layer;
a transistor 40 over the first insulating layer;
a second insulating layer 33 over the transistor, paragraph 72;
a second resin layer 34 over the second insulating layer, paragraphs 272 and 249; and
wherein the first insulating layer and the second insulating layer comprise an inorganic insulating film containing nitrogen, paragraphs 101, 102, 85, 270, 244, and 245.
Yamazaki does not disclose in the embodiment of Figure 4, wherein the transistor comprises a semiconductor layer, a first gate electrode, and a second gate electrode,
wherein the first gate electrode and the second gate electrode overlap with each other,
Yamazaki discloses in the embodiment of Figure 8B, the transistor comprises a semiconductor layer, a first gate electrode 81, a second gate electrode 85, a first gate insulating layer 82 between the semiconductor layer and the first gate electrode, and a second gate insulating layer 84 between the semiconductor layer and the second gate electrode, wherein the first gate electrode and the second gate electrode overlap with each other, paragraphs 130 and 172. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the transistor to comprise a semiconductor layer, a first gate electrode, a second gate electrode, and the first gate electrode and the second gate electrode overlap with each other. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one transistor configuration for another.
Yamazaki does not disclose a second wring over the second resin layer,
wherein the first gate electrode is electrically connected to the first wiring in an opening portion in the first insulating layer and the first resin layer,
wherein the second wiring is electrically connected to one of a source and a drain of the transistor,
wherein in a plane view, the first wiring is arranged to extend in a first direction,
wherein in the plane view, the second wiring is arranged to extend in a second direction intersecting the first direction,
wherein in the plane view, the first wiring has a region intersecting the second wiring,
wherein the region overlaps with the second wiring with the first resin layer, the first insulating layer, the second insulating layer, and the second resin layer sandwiched therebetween,
wherein the first resin layer has a lower permittivity than the first insulating layer,
wherein a thickness of the first resin layer is greater than or equal to five times and less than or equal to 100 times a thickness of the first insulating layer,
wherein the second resin layer has a lower permittivity than the second insulating layer and
wherein a thickness of the second resin layer is greater than or equal to five times and less than or equal to 100 time a thickness of the second insulating layer.
Guo et al. (US 2021/0013242) discloses a display device including teaching a first gate electrode, 151 in Figure 3, is electrically connected to the first wiring 13 in an opening portion in the first insulating layer 122 and the first resin layer 121, paragraphs 84 and 85. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first gate electrode to be electrically connected to the first wiring in an opening portion in the first insulating layer and the first resin layer. One would have been motivated to do so in order to form the gate line in a flexible substrate.
Kajiyama (US 2018/0138260), hereafter “Kajiyama,” discloses a display device including teaching a first resin layer, 72 in Figure 3, has a lower permittivity than the first insulating layer 61, paragraphs 31, 32, and 42. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first resin layer to have a lower permittivity than the first insulating layer. One would have been motivated to do so in order to suppress a capacitance between conductive layers, paragraph 42.
Sasaki et al. (US 2018/0090515), hereafter “Sasaki,” discloses a display device including teaching a thickness of a first resin layer, 530 in Figure 4, is greater than or equal to five times and less than or equal to 100 times a thickness of the first insulating layer 540, (first resin “thicker than the film thickness of the first wiring,” combined thickness of 250 nm-3.2 µm, paragraphs 70 and 71, first insulating 20 nm-1 µm, 50 nm-500 nm, paragraphs 69 and 72).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a thickness of the first resin layer to be greater than or equal to five times and less than or equal to 100 times a thickness of the first insulating layer. One would have been motivated to do so in order to provide a thick resin layer able to function as a planarization layer, paragraph 71.
Izumi et al. (US 2003/0038306), hereafter “Izumi,” discloses a display device including teaching a second wiring 6 in Figures 1 and 2 over the second resin layer 9, wherein the second wiring is electrically connected to one of a source and a drain of the transistor, paragraphs 82 and 89, the second resin layer, 9 in Figure 2, has a lower permittivity than the second insulating layer 8, paragraphs 102 and 109, and a thickness of the second resin layer is greater than or equal to five times and less than or equal to 100 time a thickness of the second insulating layer (resin 9 1-5 µm, e.g. 3 µm, paragraphs 101 and 109, insulating layer 8 0.5 µm, paragraph 109).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second wring to be over the second resin layer, wherein the second wiring is electrically connected to one of a source and a drain of the transistor, the second resin layer to have a lower permittivity than the second insulating layer and a thickness of the second resin layer to be greater than or equal to five times and less than or equal to 100 time a thickness of the second insulating layer. One would have been motivated to do so in order to suppress a capacitance between conductive layers, paragraphs 31 and 111.
Izumi further teaches wherein in a plane view, a first wiring, 2 in Figure 1, is arranged to extend in a first direction,
wherein in the plane view, the second wiring 6 is arranged to extend in a second direction intersecting the first direction,
wherein in the plane view, the first wiring has a region intersecting the second wiring, paragraph 82.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for in a plane view, a first wiring to be arranged to extend in a first direction, the second wiring to be arranged to extend in a second direction intersecting the first direction, and the first wiring has a region intersecting the second wiring. One would have been motivated to do so in order to form an array of addressable pixels, paragraph 82.
In reference to the region overlapping with the second wiring with the first resin layer, the first insulating layer, the second insulating layer, and the second resin layer sandwiched therebetween,
Guo teaches the first wiring below the first insulating layer and the first resin layer and Izumi teaches the second wiring above the second insulating layer and the second resin layer and the first wire intersecting the second wiring as addressed above. It results naturally form the combination of Yamazaki, Guo, and Izumi that the region overlaps with the second wiring with the first resin layer, the first insulating layer, the second insulating layer, and the second resin layer sandwiched therebetween.
In reference to claim 2, the combination of Yamazaki, Sasaki, and Izumi suggests the first resin layer and the second resin layer contain the same material, (acrylic or polyimide; first resin, 530 in paragraph 59 of Sasaki; second resin, 34 in paragraphs 205, 206, 249, 274 of Yamazaki) and the thickness of the second resin layer is greater than or equal to 80% and less than or equal to 120% of the thickness of the first resin layer (first resin, 530, 250 nm-3.2 µm, paragraphs 70 and 71 of Sasaki; second resin, resin 9 1-5 µm, e.g. 3 µm, paragraphs 101 and 109 of Izumi).
In reference to claim 3, the combination of Yamazaki, Sasaki, and Izumi suggests the first insulating layer 31 and the second insulating layer 33 contain the same material, paragraphs 244, 245, and 270 of Yamazaki, and a thickness of the second insulating layer is greater than or equal to 80% and less than or equal to 120% of a thickness of the first insulating layer, ( first insulating 540, 20 nm-1 µm, 50 nm-500 nm, paragraphs 69 and 72 of Sasaki; second insulating layer 8, 0.5 µm, paragraph 109 of Izumi).
In reference to claim 8, Yamazaki discloses the transistor comprises a semiconductor layer 44 and wherein the semiconductor layer contains oxygen and either one or both of indium and zinc, paragraphs 82 and 261.
In reference to claim 10, Sasaki discloses the first resin layer contains acrylic or polyimide, 530 in paragraph 59. Yamazaki discloses the second resin layer 34 contains acrylic or polyimide, paragraphs 205, 206, 249, 274.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bae et al. (US 2020/0235187), Zhou et al. (US 2022/0102462), and Wang et al. (US 11,960,180), disclose related structures with wiring lines in organic substrate layers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897