DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/31/26 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 3/31/26. Claims 1 and 4 have been amended. No new claims have been added. Currently, claims 1-2 and 4-7 are pending.
Response to Arguments
Applicant’s arguments filed 3/31/26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-2 and 4-7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites the limitation “first conductive medium layers comprising a heavily-doped polycrystalline silicon” in lines 5-6 of paragraph 1, “the first conductive medium layers each comprise a heavily-doped polycrystalline silicon” in the first two lines of paragraph 2, and “wherein the first conductive medium layers each comprise a heavily-doped polycrystalline silicon layer and a metal silicide layer” in paragraph 4. It is unclear if a heavily-doped polycrystalline silicon layer in paragraph 2 is referring back to the same heavily-doped polycrystalline silicon layer cited in paragraph 1. It is also unclear if a heavily-doped polycrystalline silicon layer in paragraph 4 is referring back to the same heavily-doped polycrystalline silicon layer cited in paragraphs 1 or 2 or a different one.
For the purposes of examination with regard to the prior art, they will be interpreted as the same heavily-doped polycrystalline silicon layer.
Claim 2, because it is dependent on claim 1, inherit the deficiency of claim 1.
Claim 4 recites the limitation “in step A” in line 18 of the claim. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, “A)” will be added before “etching a metal silicide layer” in line 16, and “B)” will be added before “filling the recess formed in step A” in line 18.
Claims 5-7, because they are dependent on claim 4, inherit the deficiency of claim 4.
Claim 6 recites “the insulating material” in the last line of step B. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, “the insulating material” in the last line of step B will be treated as “an insulating material.”
Claim 6 recites “an insulating material” in the last line of step 3.1. The scope of claim 6 is unclear because it is not clear to an ordinary artisan if “an insulating material” is the same element as “an insulating material” in the last line of step B, or if it is a second insulating material.
For the purposes of examination with regard to the prior art, “an insulating material” in the last line of step 3.1. will be treated as “a second insulating material.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (CN 109686703 A, citations made hereinafter to the English machine translation attached to the Office Action mailed on 6/17/2025) in view of Melik-Martirosian et al. (US 9741768) and Sakotsubo (US 20170141161).
Regarding claim 1, Peng teaches a three-dimensional multilayer memory (see Fig. 1, [0057]), comprising a base structure (Fig. 3, [0063]),
wherein the base structure is divided into two interdigitated structures (55/51/53 and 56/52/54) which are independent of each other by a curved division trench (50, Fig. 5, [0064]), referred to as a first interdigitated structure (55/51/53) and a second interdigitated structure (56/52/54), respectively;
the base structure comprises first conductive medium layers (11, labeled in Fig. 1, [0057]) comprising a heavily-doped polycrystalline silicon ([0061], Table 1) and insulating medium layers which are alternately stacked on each other from bottom to top (see Fig. 3, [0063]);
at least three memory cell holes (60) are disposed side by side in the curved division trench (see Fig. 6, [0065]), a vertical electrode is disposed in each memory cell hole (see Fig. 9, [0067]), and an insulating isolation pillar is disposed between two adjacent memory cell holes (see Fig. 11, [0074]);
the first conductive medium layers (11) each comprise a heavily-doped polycrystalline silicon ([0061], Table 1), the vertical electrodes ([0068], N + semiconductor or Schottky metal) and the heavily-doped polycrystalline silicon of the interdigitated structures ([0061], Table 1) as well as a storage medium ([0066]) therebetween form a memory structure;
the memory is a PN junction type semiconductor memory, a Schottky semiconductor memory, a resistance change memory, a magnetic phase change memory, a phase change memory or a ferroelectric memory ([0011], PN junction type or Schottky), and the storage medium is an insulating medium (Fig. 7, [0066]).
Peng does not explicitly teach that the base structure is disposed on an underlying circuit part, that the first conductive medium layers each comprise a heavily-doped polycrystalline silicon layer and a metal silicide layer, one stacking on top of the other; and that a recess is disposed in the metal silicide layer, close to the storage medium, and is filled with an insulating material to form an insulating region, and the insulating region is configured to isolate the metal silicide in the metal silicide layer from the storage medium, wherein a minimum thickness of the recess is 1 to 1.5 times of a thickness of the storage medium.
In a similar field of endeavor, Melik-Martirosian teaches, in Fig. 5A, that the base structure (Fig. 5C, insulating layers 514 and first conductive medium layers WL10, WL11, …, WL43; col. 16, lines 1-5) is disposed on an underlying circuit part (502; col. 15, lines 50-60);
that the first conductive medium layers (WL10, WL11, …, WL43; Figs. 5A and 5C; col. 16, lines 20-40) each comprise a first bottom conductive material layer (labelled as 406a1 in Fig. 4B; col. 11, lines 25-35; col. 12, lines 60-67; e.g., titanium nitride with more sheet resistance than 406b1) and a second top conductive material layer (labelled as 406b1 in Fig. 4B; col. 11, lines 25-35; col. 13, lines 1-5; e.g., tantalum or tantalum nitride with less sheet resistance than 406a1), one stacking on top of the other (406b1 stacking on top of 406a1); and
and that a recess (filled by 406b2, Fig. 4B) is disposed in the second conductive material layer (406b1, Fig. 4B), close to the storage medium (402, labelled as 518 in Fig. 5A; col. 11, lines 5-15; col. 26, lines 5-15), and is filled with an insulating material (406b2, labelled as 614b in Fig. 6D; col. 11, lines 20-25; col. 23, lines 5-10) to form an insulating region (406b2, Fig. 4B), and the insulating region (406b2) is configured to isolate the second top conductive material layer (406b1) from the storage medium (402) (see Fig. 4B),
wherein a minimum thickness (L2) of the recess is 10-20 angstroms (col. 11, lines 10-15),
so that “substantially all of current IX conducted between multi-layer word line 406′, memory cell 410b and vertical bit line 404 is conducted by first conductive material layer 406a′” instead of through the second conductive material layer 406b that has significantly lower sheet resistance (col. 13, lines 10-20; col. 11, lines 25-50).
It would been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the three-dimensional multilayer memory of Peng with the underlying circuit part, bilayer conductive medium layers, and the recess of Melik-Martirosian, so that the current only flows through the conductive medium layer with lower sheet resistance that does not have the thicker recess (col. 13, lines 10-20; col. 11, lines 25-50).
However, Peng in view of Melik-Martirosian does not explicitly teach that a minimum thickness of the recess is 1 to 1.5 times of a thickness of the storage medium. Nonetheless, the skilled artisan would know too that the thickness of the recess would impact the current through the conductive medium layer with the recess (Melik-Martirosian; col. 13, lines 10-20; col. 11, lines 25-50).
The specific claimed thicknesses, absent any criticality, is only considered to be the “optimum” thicknesses disclosed by Peng in view of Melik-Martirosian that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired current through the conductive medium layer with the recess, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a minimum thickness of the recess being 1 to 1.5 times of a thickness of the storage medium is used, as already suggested by Peng in view of Melik-Martirosian.
Since the applicant has not established the criticality (see next paragraph) of the thicknesses stated and since these thicknesses are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Peng in view of Melik-Martirosian.
Peng in view of Melik-Martirosian does not teach that the first conductive medium layers each comprise a heavily-doped polycrystalline silicon layer and a metal silicide layer, one stacking on top of the other.
In a similar field of endeavor, Sakotsubo teaches, in Fig. 12F, that the first conductive medium layers each comprise a heavily-doped polycrystalline silicon layer (335, [0103]) and a metal silicide layer (305, labelled as 503 in Fig. 10A, [0101]), one stacking on top of the other, in order to “alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming” and reduce voltage (Abstract, [0133]).
It would been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the three-dimensional multilayer memory of Peng in view of Melik-Martirosian with the first conductive medium layer materials of Sakotsubo, in order to alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming and to reduce voltage (Abstract, [0133]).
Regarding claim 2, Peng in view of Melik-Martirosian and Sakotsubo teaches the limitations of claim 1. Peng further teaches that a buffer layer is disposed between the vertical electrode and the storage medium (see Fig. 8, [0067]).
Regarding claim 4, Peng teaches a manufacturing method for a three-dimensional multilayer memory (see Fig. 1, [0057]), the method comprising the following steps:
forming a base structure: providing a preset number of first conductive medium layers (11, labeled in Fig. 1, [0057]) and insulating medium layers in a manner that the first conductive medium layers and the insulating medium layers are alternately stacked on each other to form the base structure (see Fig. 3, [0063]);
trenching the base structure: forming a curved division trench (50) by trenching the base structure from a top layer to a bottom layer, thus dividing the base structure into two staggered and mutually separated interdigitated structures by the division trench (55/51/53 and 56/52/54) (see Fig. 5, [0064]); and
forming a preset number of memory cell holes (60) in the division trench (see Fig. 6, [0065]),
providing an insulating medium between the adjacent memory cell holes (see Fig. 11, [0065]),
disposing a vertical electrode in each memory cell hole (see Fig. 9, [0068], and
providing a storage medium layer between the vertical electrode and the interdigitated structure (see Fig. 7, [0066]),
wherein the vertical electrode, the storage medium and the first conductive medium are all made of materials conforming to the materials required by the preset memory ([0068], vertical electrode either N + semiconductor or Schottky metal; storage medium is dielectric [0066]; conductive medium [0061], Table 1), and
the memory is a PN junction type semiconductor memory, a Schottky semiconductor memory, a resistance change memory, a magnetic phase change memory, a phase change memory, or a ferroelectric memory ([0011], PN junction type or Schottky).
Peng does not explicitly teach that in step 1), the first conductive medium layers each comprise a heavily-doped polycrystalline silicon layer and a metal silicide layer, one stacking on top of the other; and after step 2) and before step 3), the method further comprises the following steps: A) etching a metal silicide layer on an inner wall of the division trench to form a recess: and B) filling the recess formed in step A with an insulating material, wherein a minimum thickness of the recess is 1 to 1.5 times of a thickness of the storage medium.
In a similar field of endeavor, Melik-Martirosian teaches that after step 2) (see Fig. 6C; col. 24, lines 20-25) and before step 3) (see Fig. 6H1; col. 23, lines 60-65), the method further comprises the following steps:
A) etching a second conductive material layer (labelled as 406b1 in Fig. 4B; col. 11, lines 25-35; col. 13, lines 1-5; e.g., tantalum or tantalum nitride with less sheet resistance than 406a1) on an inner wall of the division trench to form a recess (700) (see Fig. 7A; col. 24, lines 15-30); and
B) filling the recess formed in step A with an insulating material (706) (see Fig. 7C; col. 24, lines 35-45), wherein a minimum thickness (L2) of the recess is 10-60 angstroms (col. 24, lines 20-30),
so that “substantially all of current IX conducted between multi-layer word line 406′, memory cell 410b and vertical bit line 404 is conducted by first conductive material layer 406a′” instead of through the second conductive material layer 406b that has significantly lower sheet resistance (col. 13, lines 10-20; col. 11, lines 25-50).
It would been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify method of forming the three-dimensional multilayer memory of Peng forming and filling of the recess of Melik-Martirosian, so that the current only flows through the conductive medium layer with lower sheet resistance that does not have the thicker recess (col. 13, lines 10-20; col. 11, lines 25-50).
However, Peng in view of Melik-Martirosian does not explicitly teach that a minimum thickness of the recess is 1 to 1.5 times of a thickness of the storage medium. Nonetheless, the skilled artisan would know too that the thickness of the recess would impact the current through the conductive medium layer with the recess (Melik-Martirosian; col. 13, lines 10-20; col. 11, lines 25-50).
The specific claimed thicknesses, absent any criticality, is only considered to be the “optimum” thicknesses disclosed by Peng in view of Melik-Martirosian that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired current through the conductive medium layer with the recess, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a minimum thickness of the recess being 1 to 1.5 times of a thickness of the storage medium is used, as already suggested by Peng in view of Melik-Martirosian.
Since the applicant has not established the criticality (see next paragraph) of the thicknesses stated and since these thicknesses are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Peng in view of Melik-Martirosian.
Peng in view of Melik-Martirosian does not teach that in step 1), the first conductive medium layers each comprise a heavily-doped polycrystalline silicon layer and a metal silicide layer, one stacking on top of the other.
In a similar field of endeavor, Sakotsubo teaches that in step 1) (see Fig. 10A, [0100]), the first conductive medium layers each comprise a heavily-doped polycrystalline silicon layer (335, [0103]) and a metal silicide layer (503, labelled as 305 in Fig. 12F, [0101]), one stacking on top of the other, in order to “alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming” and reduce voltage (Abstract, [0133]).
It would been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the three-dimensional multilayer memory of Peng in view of Melik-Martirosian with the first conductive medium layer materials of Sakotsubo, in order to alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming and to reduce voltage (Abstract, [0133]).
Regarding claim 5, Peng in view of Melik-Martirosian and Sakotsubo teaches the limitations of claim 4. Peng further teaches wherein in step 3), the memory cell hole (60) is a through hole penetrating through the base structure (see Fig. 3, [0063]).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (CN 109686703 A, citations made hereinafter to the English machine translation attached to the Office Action mailed on 6/17/2025) in view of Melik-Martirosian et al. (US 9741768) and Sakotsubo (US 20170141161), and further in view of Lee et al. (US 9356031).
Regarding claim 6, Peng in view of Melik-Martirosian and Sakotsubo teaches the limitations of claim 4. Melik-Martirosian further teaches that step B) comprises the following step: filling the division trench as well as the recess (700) formed in step A (Fig. 7A) with the insulating material (704; col. 24, lines 25-30) (see Fig. 7B); and
step 3) comprises the following steps:
3.1 vertically etching the filled insulating medium (704) until the inner wall of the division trench is exposed, thus forming the memory cell holes disposed side by side along the division trench (see Fig. 7C).
Peng further teaches that step 3) comprises the following steps:
3.1 wherein an insulating material is provided between the adjacent memory cell holes (see Fig. 11, [0074]);
3.2 depositing the insulating material on the inner wall of each memory cell hole as the storage medium (see Fig. 7, [0066]);
3.3 depositing a buffer material on the inner wall of each memory cell hole (see Fig. 8, [0067]); and
3.5. filling each memory cell hole with a vertical electrode material (see Fig. 9, [0068]).
Peng in view of Melik-Martirosian and Sakotsubo does not teach 3.4. removing the insulating material and the buffer material at a bottom region of each memory cell hole to expose the underlying circuit.’
In a similar field of endeavor, Lee teaches, in Fig. 5K, 3.4. removing the insulating material (11; col. 6, lines 45-50) and the buffer material (531; col. 9, lines 50-60) at a bottom region of each memory cell hole to expose the underlying circuit (100 and 511; col. 5, lines 25-35; col. 8, lines 1-10), in order to “make a NAND string 150 having improved performance and scalability with respect to conventional devices” (col. 7, lines 5-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method of Peng in view of Melik-Martirosian and Sakotsubo with the removing of Lee, in order to make a NAND string having improved performance and scalability with respect to conventional devices.
Regarding claim 7, Peng in view of Melik-Martirosian and Sakotsubo teaches the limitations of claim 4. Melik-Martirosian further teaches that step B) comprises the following step: depositing an insulating material (704; col. 24, lines 25-30) on the inner wall of the division trench to fill the recess (700) formed in step A (Fig. 7A) at the same time (see Fig. 7B); and
step 3) comprises the following steps:
3.1. removing the insulating material (704, Fig. 7B) covered on the inner wall of the division trench, and retaining the insulating material (706) filled in the recess (see Fig. 7C; col. 24, lines 35-40).
Peng further teaches that step 3) comprises the following steps:
3.2 depositing the insulating material on the inner wall of each memory cell hole as the storage medium (see Fig. 7, [0066]);
3.3 depositing a buffer material on the inner wall of each memory cell hole (see Fig. 8, [0067]);
3.5. filling each memory cell hole with a vertical electrode material (see Fig. 9, [0068]);
3.6. vertically etching the vertical electrode material and the buffer material filled in the division trench so as to form various independent vertical electrodes separated by isolation holes (Fig. 10, [0074]); and
3.7. filling the isolation holes with the insulating material (Fig. 11, [0075]).
Peng in view of Melik-Martirosian and Sakotsubo does not explicitly teach 3.4. removing the insulating material and the buffer material at the bottom region corresponding to the position of a circuit connection point in the division trench so as to expose the underlying circuit.
In a similar field of endeavor, Lee teaches, in Fig. 5K, 3.4. removing the insulating material (11; col. 6, lines 45-50) and the buffer material (531; col. 9, lines 50-60) at the bottom region corresponding to the position of a circuit connection point (511; col. 8, lines 1-10) in the division trench so as to expose the underlying circuit (100; col. 5, lines 25-35), in order to “make a NAND string 150 having improved performance and scalability with respect to conventional devices” (col. 7, lines 5-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method of Peng in view of Melik-Martirosian and Sakotsubo with the removing of Lee II, in order to make a NAND string having improved performance and scalability with respect to conventional devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached on 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights