DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 3/29/26. Claims 1-21, and 23-25 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 2/26/26 and 4/29/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The indicated allowability of claims 1-7 and 23-25 is withdrawn in view of the newly discovered reference(s) to McFarlane et al. (US PGPub 2024/0072212, hereinafter referred to as “McFarlane”). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-21, and 23-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McFarlane et al. (US PGPub 2024/0072212, hereinafter referred to as “McFarlane”, IDS reference).
McFarlane discloses the semiconductor device as claimed. See figures 1-12 and corresponding text, where McFarlane teaches, in claim 1, a light-emitting diode (LED) package comprising: (figure 1; [0037], [0046-0051])
a submount comprising a first face and a second face that opposes the first face;at least one LED chip on the first face of the submount; a cover structure arranged over the at least one LED chip; a patterned trace on the first face of the submount, the cover structure being only attached to a first portion of the patterned trace at a cover structure mounting area that is outside a second portion of the patterned trace forming at least one die attach pad, wherein the first portion of the patterned trace is discontinuous with the second portion of the patterned trace; Anda dielectric reflector on the first portion of the patterned trace that is between the at least one die attach pad and the cover structure mounting area, the dielectric reflector comprising a distributed Bragg reflector.
McFarlane teaches, in claim 2. (Original) The LED package of claim 1, wherein the distributed Bragg reflector is an aperiodic distributed Bragg reflector (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 3. (Original) The LED package of claim 2, wherein: the aperiodic distributed Bragg reflector comprises a plurality of dielectric layers; and each dielectric layer of the plurality of dielectric layers comprises a unique optical thickness relative to other dielectric layers of the plurality of dielectric layers (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 4. (Original) The LED package of claim 3, wherein the plurality of dielectric layers comprises alternating dielectric layers of a first material type and a second material type (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 5. (Original) The LED package of claim 1, wherein the dielectric reflector is further on a portion of the submount that is uncovered by the patterned trace and the at least one LED chip (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 6. (Original) The LED package of claim 5, wherein the dielectric reflector is further arranged between the at least one LED chip and the submount in a gap formed by the patterned trace along the at least one die attach pad (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 7. (Original) The LED package of claim 6, wherein the at least one LED chip is configured to provide a peak wavelength in a range from 200 nm to 400 nm (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 8. (Currently Amended) A light-emitting diode (LED) package comprising: (figure 1; [0037], [0046-0051])
a submount comprising a first face and a second face that opposes the first face;at least one LED chip on the first face of the submount; a cover structure arranged over the at least one LED chip, the cover structure being only mounted to the submount at a cover structure mounting area that is spaced from a peripheral boundary of the at least one LED chip; a patterned trace on the first face of the submount, the patterned trace forming at least one die attach pad, and for the at least one LED chip is mounted to the die attach pad; Anda dielectric reflector on a portion of the submount that is laterally adjacent the patterned trace, the dielectric reflector comprising a distributed Bragg reflector.
McFarlane teaches, in claim 9. (Original) The LED package of claim 8, wherein the dielectric reflector is further arranged on a portion of the patterned trace (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 10. (Original) The LED package of claim 8, wherein the dielectric reflector is further arranged between the cover structure and the submount at the cover structure mounting area (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 11. (Original) The LED package of claim 8, wherein: the distributed Bragg reflector is an aperiodic distributed Bragg reflector; the aperiodic distributed Bragg reflector comprises a plurality of dielectric layers; and each dielectric layer of the plurality of dielectric layers comprises a unique optical thickness relative to other dielectric layers of the plurality of dielectric layers (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 12. (Original) The LED package of claim 11, wherein the plurality of dielectric layers comprises alternating dielectric layers of a first material type and a second material type (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 13. (Original) The LED package of claim 11, wherein a dielectric layer with a largest optical thickness of the plurality of dielectric layers is positioned to be spaced away from a top surface of the aperiodic distributed Bragg reflector and within an interior of the aperiodic distributed Bragg reflector (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 14. (Original) The LED package of claim 8, wherein the at least one LED chip is configured to provide a peak wavelength in a range from 200 nm to 400 nm (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 15. (Currently Amended) A light-emitting diode (LED) package comprising: (figure 1; [0037], [0046-0051])
a submount comprising a first face and a second face that opposes the first face;at least one LED chip on the first face of the submount; a patterned trace on the first face of the submount; a cover structure attached to the submount to form a cavity separating the cover structure from the at least one LED chip; Anda dielectric reflector on a portion of the patterned trace within the cavity and on a portion of the submount that is laterally adjacent the patterned trace within the cavity, the dielectric reflector comprising a distributed Bragg reflector.
McFarlane teaches, in claim 16, wherein the distributed Bragg reflector is an aperiodic distributed Bragg reflector (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 17, wherein: the aperiodic distributed Bragg reflector comprises a plurality of dielectric layers; and each dielectric layer of the plurality of dielectric layers comprises a unique optical thickness relative to other dielectric layers of the plurality of dielectric layers (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 18, wherein the plurality of dielectric layers comprises alternating dielectric layers of a first material type and a second material type (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 19, wherein a dielectric layer with a largest optical thickness of the plurality of dielectric layers is positioned to be spaced away from a top surface of the aperiodic distributed Bragg reflector and within an interior of the aperiodic distributed Bragg reflector (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 20, wherein: the patterned trace comprises at least one die attach pad for the at least one LED chip; and the dielectric reflector is further arranged between the at least one LED chip and the submount in a gap formed by the patterned trace along the at least one die attach pad (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 21, wherein the at least one LED chip is configured to provide a peak wavelength in a range from 200 nm to 400 nm (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 23, further comprising a reflector structure arranged between the cover structure and the submount, wherein a sidewall of the reflector structure bounds a portion of the cavity (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 24, wherein the dielectric reflector is arranged on the sidewall of the reflector structure (figure 1; [0037], [0046-0051]).
McFarlane teaches, in claim 25, wherein the dielectric reflector is arranged between the reflector structure and the submount (figure 1; [0037], [0046-0051]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-21, and 23-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 May 31, 2026
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