DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on December 29, 2025 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 29, 2025.
Drawings
The drawings are objected to because [0029] refers to bitline contacts 304 and bitline airgaps 302 but Fig 3 appears to be pointing to the wrong parts. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “55” of Fig 3 has been used to designate both a bitline and an airgap. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: [0056] and [0058] disclose NAND 946. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
-Fig 3 reference characters 41, 42, and 55
-Figs 4, 5, and 6 reference characters 41, 42 and W (associated with a bitline)
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuno et. al. (US 11387142 B1), hereinafter Matsuno.
Regarding claim 1, Matsuno teaches a memory die (not shown semiconductor die, [col 6, lines 12-23]) comprising: a memory array (Fig 15B memory array region 100, [col 27, line 11]); and a bitline structure (Fig 26B structure with bitlines 118, material layer 122, material layer 126, and air gap 229) coupled to the memory array (Fig 15B memory array region 100, [col 27, line 11]), the bitline structure (Fig 26B structure with bit lines 118, material layer 122, material layer 126, and air gap 229) comprising: a plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); a dielectric layer (Fig 26B material layer 122 [col 33, line 41]) position above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); an air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) positioned above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); and an air gap (Fig 26B air gap 229 [col 34, line 51]) positioned between adjacent bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]), wherein the air gap (Fig 26B air gap 229 [col 34, line 51]) has an air gap height dimension (total height of air gap 229) that extends past a bitline contact height dimension (total height of bitline contact 118) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]).
Regarding claim 2, Matsuno teaches the air gap (Fig 26B air gap 229 [col 34, line 51]) extends into the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]).
Regarding claim 4, Matsuno teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]) comprise one or more of tungsten, aluminum, copper (copper, [col 26, lines 49-53]), and molybdenum.
Regarding claim 5, Matsuno teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]) are constructed through a subtractive bitline formation process ([col 27, lines 9-11]).
The language, term, or phrase “the plurality of bitline contacts are constructed through a subtractive bitline formation process”, is directed towards the process of making the plurality of bitline contacts. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the plurality of bitline contacts are constructed through a subtractive bitline formation process” only requires the plurality of bitline contacts, which does not distinguish the invention from Matsuno, who teaches the structure as claimed.
Regarding claim 6, Matsuno teaches the memory die (not labeled, [col 4, lines 12-23]) comprises 3D-NAND memory ([col 40, lines 21-24]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuno et. al. (US 11387142 B1), hereinafter Matsuno.
Regarding claim 3, Matsuno teaches the air gap height dimension (total height of air gap 229) extends past (the top end of the air gap 229 may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) a dielectric layer (Fig 26B material layer 122 [col 33, line 41]) height dimension of the dielectric layer (Fig 26B material layer 122 [col 33, line 41]).
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuno et. al. (US 11387142 B1), hereinafter Matsuno, in view of Lim et. al. (US 20190164991 A1), hereinafter Lim.
Regarding claim 7, Matsuno teaches the memory device (not shown semiconductor package, [col 6, lines 12-23]) comprising: a memory array (Fig 15B memory array region 100, [col 27, line 11]); and a bitline structure (Fig 26B structure with bitlines 118, material layer 122, material layer 126, and air gap 229) coupled to the memory array (Fig 15B memory array region 100, [col 27, line 11]), the bitline structure (Fig 26B structure with bitlines 118, material layer 122, material layer 126, and air gap 229) comprising: a plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]); a dielectric layer (Fig 26B material layer 122 [col 33, line 41]) position above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]); an air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) positioned above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); and an air gap (Fig 26B air gap 229 [col 34, line 51]) positioned between adjacent bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]), wherein the air gap (Fig 26B air gap 229 [col 34, line 51]) has an air gap height dimension (total height of air gap 229) that extends past a bitline contact height dimension (total height of bitline contact 118) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]).
Matsuno fails to teach a solid state drive (SSD) comprising: a memory controller; and a memory device coupled to the memory controller.
However, Lim teaches a solid state drive (SSD) (Fig 15 solid-state drive system 1000, [0121]) comprising: a memory controller (Fig 15 SSD controller 1210, [0123]); and a memory device (Fig 15 memory device 1230, 1240, 1250, [0123] corresponds to Matsuno: not shown semiconductor package, [col 6, lines 12-23]) coupled to the memory controller (Fig 15 SSD controller 1210, [0123]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Matsuno to incorporate the teachings of Lim by having the memory device of Matsuno be used in a system as taught by Lim. This would provide further commercial uses for the memory device of Lim.
Regarding claim 8, Matsuno as modified in claim 7 teaches the air gap (Fig 26B air gap 229 [col 34, line 51]) extends into the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]).
Regarding claim 9, Matsuno as modified in claim 7 teaches the air gap height dimension (total height of air gap 229) extends past (the top end of the air gap 229 may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) a dielectric layer (Fig 26B material layer 122 [col 33, line 41]) height dimension of the dielectric layer (Fig 26B material layer 122 [col 33, line 41]).
Regarding claim 10, Matsuno as modified in claim 7 teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) comprise one or more of tungsten, aluminum, copper (copper, [col 26, lines 49-53]), and molybdenum.
Regarding claim 11, Matsuno as modified in claim 7 teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) are constructed through a subtractive bitline formation process ([col 27, lines 9-11]).
The language, term, or phrase “the plurality of bitline contacts are constructed through a subtractive bitline formation process”, is directed towards the process of making the plurality of bitline contacts. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the plurality of bitline contacts are constructed through a subtractive bitline formation process” only requires the plurality of bitline contacts, which does not distinguish the invention from Matsuno, who teaches the structure as claimed.
Regarding claim 12, Matsuno as modified in claim 7 teaches the memory device (not shown semiconductor package, [col 6, lines 12-23]) comprises 3D-NAND memory ([col 40, lines 21-24]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hopkins et. al. (US 20220051991 A1) teaches air gaps between bit lines with a two different
dielectric layers on top of the bit lines.
Sim et. al. (US 20120058639 A1) teaches the height of top of air gaps can be adjusted depending on growth parameters. Further, Sim teaches the bit line material can be made of metal as an example tungsten, aluminum, or copper.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813