DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed June 22, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Drawings have overcome each and every objection previously set forth in the Non-Final Office Action mailed March 09, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuno et. al. (US 11387142 B1), hereinafter Matsuno.
Regarding claim 1, Matsuno teaches a memory die (not shown semiconductor die, [col 6, lines 12-23]) comprising: a memory array (Fig 15B memory array region 100, [col 27, line 11]); and a bitline structure (Fig 26B structure with bitlines 118, material layer 122, material layer 126, and air gap 229) coupled to the memory array (Fig 15B memory array region 100, [col 27, line 11]), the bitline structure (Fig 26B structure with bit lines 118, material layer 122, material layer 126, and air gap 229) comprising: a plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); a first dielectric layer (Fig 26B material layer 122 [col 33, line 41]) positioned above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); an air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) positioned above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); and an air gap (Fig 26B air gap 229 [col 34, line 51]) positioned between adjacent bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]), wherein the air gap (Fig 26B air gap 229 [col 34, line 51]) has an air gap height dimension (total height of air gap 229) that extends past a bitline contact height dimension (total height of bitline contact 118) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); wherein the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) includes a recess (See annotated figure), and the recess (See annotated figure) starts from an interface (See annotated figure) between the first dielectric layer (Fig 26B material layer 122 [col 33, line 41]) and the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49])and extends into (the top end of the air gap 229/recess may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]).
PNG
media_image1.png
878
713
media_image1.png
Greyscale
Regarding claim 2, Matsuno teaches both the the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) and the first dielectric layer (Fig 26B material layer 122 [col 33, line 41]) are made of a first type of dielectric material (layer 122 is silicon oxide, [col 29, lines 29-32]; layer 124 is silicon oxide, [col 30, lines 18-27]).
Regarding claim 4, Matsuno teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]) comprise one or more of tungsten, aluminum, copper (copper, [col 26, lines 49-53]), and molybdenum.
Regarding claim 5, Matsuno teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]) are constructed through a subtractive bitline formation process ([col 27, lines 9-11]).
The language, term, or phrase “the plurality of bitline contacts are constructed through a subtractive bitline formation process”, is directed towards the process of making the plurality of bitline contacts. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the plurality of bitline contacts are constructed through a subtractive bitline formation process” only requires the plurality of bitline contacts, which does not distinguish the invention from Matsuno, who teaches the structure as claimed.
Regarding claim 6, Matsuno teaches the memory die (not labeled, [col 4, lines 12-23]) comprises 3D-NAND memory ([col 40, lines 21-24]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuno et. al. (US 11387142 B1), hereinafter Matsuno.
Regarding claim 3, Matsuno teaches the air gap height dimension (total height of air gap 229) extends successively past (the top end of the air gap 229 may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) the bitline contact height dimension (Fig 26B) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]), a dielectric layer (Fig 26B material layer 122 [col 33, line 41]) height dimension of the first dielectric layer (Fig 26B material layer 122 [col 33, line 41]), and at least a part of a height dimension (the top end of the air gap 229 may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) of the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]).
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuno et. al. (US 11387142 B1), hereinafter Matsuno, in view of Lim et. al. (US 20190164991 A1), hereinafter Lim.
Regarding claim 7, Matsuno teaches the memory device (not shown semiconductor package, [col 6, lines 12-23]) comprising: a memory array (Fig 15B memory array region 100, [col 27, line 11]); and a bitline structure (Fig 26B structure with bitlines 118, material layer 122, material layer 126, and air gap 229) coupled to the memory array (Fig 15B memory array region 100, [col 27, line 11]), the bitline structure (Fig 26B structure with bitlines 118, material layer 122, material layer 126, and air gap 229) comprising: a plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]); a first dielectric layer (Fig 26B material layer 122 [col 33, line 41]) positioned above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) (Fig 26B bit lines 118, [col 33, line 26]); an air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) positioned above the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); and an air gap (Fig 26B air gap 229 [col 34, line 51]) positioned between adjacent bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]), wherein the air gap (Fig 26B air gap 229 [col 34, line 51]) has an air gap height dimension (total height of air gap 229) that extends past a bitline contact height dimension (total height of bitline contact 118) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]); wherein the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) includes a recess (See annotated figure of claim 1), and the recess (See annotated figure) starts from an interface (See annotated figure of claim 1) between the first dielectric layer (Fig 26B material layer 122 [col 33, line 41]) and the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) and extends into (the top end of the air gap 229/recess may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]).
Matsuno fails to teach a solid state drive (SSD) comprising: a memory controller; and a memory device coupled to the memory controller.
However, Lim teaches a solid state drive (SSD) (Fig 15 solid-state drive system 1000, [0121]) comprising: a memory controller (Fig 15 SSD controller 1210, [0123]); and a memory device (Fig 15 memory device 1230, 1240, 1250, [0123] corresponds to Matsuno: not shown semiconductor package, [col 6, lines 12-23]) coupled to the memory controller (Fig 15 SSD controller 1210, [0123]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Matsuno to incorporate the teachings of Lim by having the memory device of Matsuno be used in a system as taught by Lim. This would provide further commercial uses for the memory device of Lim.
Regarding claim 8, Matsuno as modified in claim 7 teaches both the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]) and the first dielectric layer (Fig 26B material layer 122 [col 33, line 41]) are made of a first type of dielectric material selected from oxide (layer 122 is silicon oxide, [col 29, lines 29-32]; layer 124 is silicon oxide, [col 30, lines 18-27]), nitride (optional so not considered), and a combination of oxide and nitride (optional so not considered).
Regarding claim 9, Matsuno as modified in claim 7 teaches the air gap height dimension (total height of air gap 229) extends successively past (the top end of the air gap 229 may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) the bitline contact height dimension (Fig 26B) of the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26])s, a dielectric layer (Fig 26B material layer 122 [col 33, line 41]) height dimension of the first dielectric layer (Fig 26B material layer 122 [col 33, line 41]), and at least a part of a height dimension (the top end of the air gap 229 may extend above the bottom surface of the material layer 126, [col 32, lines 24-29]) of the air gap dielectric layer (Fig 26B material layer 124 [col 33, line 49]).
Regarding claim 10, Matsuno as modified in claim 7 teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) comprise one or more of tungsten, aluminum, copper (copper, [col 26, lines 49-53]), and molybdenum.
Regarding claim 11, Matsuno as modified in claim 7 teaches the plurality of bitline contacts (Fig 26B bit lines 118, [col 33, line 26]) are constructed through a subtractive bitline formation process ([col 27, lines 9-11]).
The language, term, or phrase “the plurality of bitline contacts are constructed through a subtractive bitline formation process”, is directed towards the process of making the plurality of bitline contacts. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the plurality of bitline contacts are constructed through a subtractive bitline formation process” only requires the plurality of bitline contacts, which does not distinguish the invention from Matsuno, who teaches the structure as claimed.
Regarding claim 12, Matsuno as modified in claim 7 teaches the memory device (not shown semiconductor package, [col 6, lines 12-23]) comprises 3D-NAND memory ([col 40, lines 21-24]).
Response to Arguments
Applicant's arguments, see 35 USC §102 section starting on page 7, filed June 22, 2026, with
respect to the amendments to claim 1, have been fully considered but they are not persuasive.
While Matsuno is silent on the features in the argument, Matsuno teaches capping layer 126 is formed on material layer 122 ([col 34, lines 39-59]). The downward-protruding portions 126P would naturally form an interface between the two layers. Further, a recess (air gap/via-level cavity 229) would start at the previously mentioned interface as shown in the figures presented by Applicant on page 7.
Applicant's arguments, see 35 USC §103 section starting on page 8, filed June 22, 2026, with
respect to the amendments to claim 7, have been fully considered but they are not persuasive.
Similar to the reply for claim 1, while Matsuno is silent on the features in the argument, Matsuno teaches capping layer 126 is formed on material layer 122 ([col 34, lines 39-59]). The downward-protruding portions 126P would naturally form an interface between the two layers. Further, a recess (air gap/via-level cavity 229) would start at the previously mentioned interface as shown in the figures presented by Applicant on page 7.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights