DETAILED ACTION
This action is responsive to the following communications: the Application filed October 17, 2022.
Claims 1-20 are pending. Claims 1, 11 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-7, 11, 14, 16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2022/0172790).
Regarding independent claims 1, 11 and 16, Lee et al. disclose a memory device (see FIG. 1) comprising:
a memory array including a local word line circuit (160) and a plurality of local word lines (L_WLs) coupled to the local word line circuit;
a word line (WL) sense circuit (130, 140, 150, also see FIG. 5: 140) coupled to an access node (BLKWL0-1, also see FIG. 2: BLKWL0) in the local word line circuit, the WL sense circuit to sense a voltage level in the local word line circuit while bypassing a disturbance to operation of the local word lines (see e.g., para. 0031: When an operation being performed currently is completed, … discharge the high voltage …, para. 0038: … the high voltage … is to be rapidly discharged before an operating on …; i.e., bypassing a disturbance) and to provide an output signal that indicates when the voltage level has reached a high voltage threshold value to enable a read operation (see FIG 1, along with FIGS. 2-3 and 5); and
read logic coupled to the WL sense circuit (130, 140, 150), the read logic to:
receive the output signal (BLKWL0-1) from the WL sense circuit; and
trigger a read operation for one or more cells in the memory array when the output signal indicates that the voltage level has reached the high voltage threshold value (i.e., the output signal BLKWL0-1 triggers a read operation of memory cell 110 when the output signal BLKWL0 is high enough (see FIG. 5) to trigger L_WL to operate memory read operation, see FIGS. 1-3 and 5, and accompanying disclosure).
Regarding claims 6, 14 and 18, which depends from claims 1, 11 and 16, respectively, Lee et al. disclose the memory array (FIG. 1) includes a plurality of planes (110A and 110B), wherein each plane includes a local word line circuit,(L_WL) and wherein for each plane one of a plurality of WL sense circuits (140 and 150) is coupled to an access node in the respective local word line circuit (see FIG. 1).
Regarding claim 7, which depends from claim 1, Lee et al. disclose a switch coupled to the WL sense circuit and to a plurality of access nodes in the local word line circuit, wherein the switch connects an input of the WL sense circuit to one of the plurality of access nodes (FIGS. 1-3 and 5, and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 8-9, 12 and 17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0172790) in view of e.g., Chen (US 2023/0386524).
Regarding claims 2, 12 and 17, Lee et al. teach the limitations of claims 1, 11, and 16, respectively.
Lee et al. are silent with respect to the WL sense circuit includes a comparator to compare the voltage level with the high voltage threshold, and wherein the high voltage threshold is set based on a low voltage reference.
However, voltage generating circuit having a comparator is a well-known technology for a type of memory control circuit for its purpose.
For support, of the above asserted facts, see for example, Chen (US 2023/0386524), e.g., FIG. 4 and accompanying disclosure, i.e., word line voltage circuit having a comparator to compares word line voltages and a low reference voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a voltage comparator providing word line voltage because these conventional technology are well established in the art of the memory devices.
Regarding claim 3, Lee et al. and Chen, as combined, teach the limitations of claim 2.
Lee and Chen do not explicitly disclose teaches the low voltage reference is tuned to provide a high voltage threshold optimized for read operations.
However the claimed limitation of optimizing voltage for read operation is a well-known technology in a memory circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a optimized voltage providing word line voltage because these conventional technology are well established in the art of the memory devices.
Regarding claim 8, Lee et al. and Chen, as combined, teach the limitations of claim 2.
Lee et al. further teach a high voltage input line for an externally supplied high voltage (e.g., para. 0046: …HVN2 may receive an external voltage VEXT …; further this is a well-known technology).
Regarding claim 9, Lee et al. and Chen, as combined, teach the limitations of claim 8.
Lee and Chen do not explicitly disclose the externally supplied high voltage is to be in a range of 10 to 12 volts, wherein the low voltage reference is to be in a range of 0.2 to 1.0 volts, and wherein the high voltage threshold is to be in a range of 6 to 7 volts.
However the claimed limitation of voltage range is a well-known technology in a memory circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a voltage range providing word line voltage because these conventional technology are well established in the art of the memory devices.
Claims 10, 15 and 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0172790) in view of e.g., Nge (US 2018/0189223).
Regarding claims 10 and 20, Lee et al. teach the limitations of claims 1 and 16, respectively.
Lee et al. are silent with respect to the read logic is to bypass use of an open loop timer signal for triggering the read operation.
However the claimed limitation is a well-known technology in a memory circuit.
For support, of the above asserted facts, see for example, Nge, e.g., FIG. 4 and accompanying disclosure, i.e., enabling bypass power path response timer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize read logic for read operation because these conventional technology are well established in the art of the memory devices.
Regarding claim 15, Lee et al. teach the limitations of claim 11.
Lee et al. further teach logic coupled to the substrate1, wherein the logic is implemented at least partly in one or more of configurable or fixed- functionality hardware, the logic to: receive the output signal from the WL sense circuit; and trigger a read operation for one or more cells in the memory array when the output signal indicates that the voltage level has reached the high voltage threshold value (see FIG 1, along with FIGS. 2-3 and 5).
Lee et al. are silent with respect to the logic is to bypass use of an open loop timer signal for triggering the read operation.
However the claimed limitation is a well-known technology in a memory circuit.
For support, of the above asserted facts, see for example, Nge, e.g., FIG. 4 and accompanying disclosure, i.e., enabling bypass power path response timer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize read logic for read operation because these conventional technology are well established in the art of the memory devices.
Allowable Subject Matter
Claims 4-5, 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Known knowledge in semiconductor manufacturing.