DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under U.S.C. 103 as being unpatentable over Campanella-Pineda et al.; US 2021/0010971 A1; 07/2019 in view of Veiseh et al.; US 2020/0101455 A1; 10/2019
Claim 1: Campanella-Pineda discloses a structure ( Fig. 6 structure #10 ), comprising: a semiconductor substrate ( Fig. 6 substrate #18 ); an insulating layer ( Fig. 6 insulator layer #16 ) on the semiconductor substrate ( Fig. 6 substrate #18); a device layer ( Fig. 6 device layer #14 ) on the insulating layer ( Fig. 6 insulator layer #16 ), wherein a cavity ( Fig. 6 cavity #52 ) extends from the device layer ( Fig. 6 device layer #14 ) through the insulator layer ( Fig. 6 insulator layer #16 ) and into the semiconductor substrate ( Fig. 6 substrate #18 ); and an ion-sensitive field effect transistor ( Fig. 6 #22 ) in the device layer ( [0022] the field-effect transistor #22 may be fabricated by front-end-of the line processing using the active region of the device layer #14) positioned over the cavity ( Fig. 6 #52 ).
Campanella-Pineda does not appear to disclose the semiconductor substrate includes an insulating material window extending to the cavity and wherein the insulating material window is between portions of semiconductor material of the one of the device layer and the semiconductor substrate along a surface of the cavity.
However, Veiseh teaches the semiconductor substrate ( Fig. 27 #154 ) includes an insulating material window ( Fig. 27 #168 ) extending to the cavity ( Fig. 27 #162-1 ) and wherein the insulating material window ( Fig. 27 #168 ) is between portions of semiconductor material of the one of the device layer ( Fig. 27 #156’ ) and the semiconductor substrate ( Fig. 27 #154 ) along a surface of the cavity ( Fig. 27 #162-1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Veiseh with Campanella-Pineda to implement the semiconductor substrate includes an insulating material window extending to the cavity and wherein the insulating material window is between portions of semiconductor material of the one of the device layer and the semiconductor substrate along a surface of the cavity because this configuration prevents unwanted electrical paths that could cause crosstalk or interference.
Claim 2: Campanella-Pineda and Veiseh disclose the structure according to claim 1 (as discussed above).
Campanella-Pineda teaches the insulating material window ( Fig. 6 #30) includes a layer of insulating material ( [0025] The anchor #30 may be formed by filling the trench #28 with a material, such as silicon nitride, aluminum nitride, or aluminum oxide. - These materials are insulators ) that fills an opening to the cavity ( [0033] the anchor #30 provides an etch stop for the etching process and defines or delimits an outer boundary of the cavity #52 ), and wherein the opening one of: extends vertically through the device layer to the cavity ( Fig. 3A #32 is cast in the opening to the cavity #28); extends vertically from a bottom of the semiconductor substrate to the cavity ( [ 0026] the anchor #30 may extend fully through the buried insulator layer #16 and to a shallow depth into the substrate #18), and extends laterally from a side of the semiconductor substrate to the cavity ( [0034] The anchor #30 is laterally positioned between, and adjacent to, the cavity).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Campanella-Pineda et al.; US 2021/0010971 A1; 07/2019 in view of Veiseh et al.; US 2020/0101455 A1; 10/2019 as it relates to claim 1 and further in view of Wolf et al.; US 6,277,629 B1 ; 06/2000.
Claim 3: Campanella-Pineda and Veiseh disclose the structure according to claim 1 (as discussed above).
Neither Campanella-Pineda nor Veiseh appear to disclose the insulating material window directs light from a light source into the cavity.
Wolf teaches the insulating material window (Fig 2, #15) directs light from a light source into the cavity (Col 4, lines 5-7 Through the window, the cells can instead be irradiated with light).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Wolf with Campanella-Pineda and Veiseh to implement the insulating material window directs light from a light source into the cavity because the window can reduce unwanted reflections and also confine or redirect light for improved performance or efficiency.
Claim 4: Campanella-Pineda, Veiseh, and Wolf disclose the structure according to claim 3 (as discussed above).
Neither Campanella-Pineda nor Veiseh appear to disclose the light source includes a tunable laser.
However, Wolf teaches the light source includes a tunable laser ( Col. 4 lines 5-7 Through the window, the cells can instead be irradiated with light, for example with laser light).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Wolf with Campanella-Pineda, and Veiseh to implement the light source includes a tunable laser because the wavelength of the emitted light can be precisely controlled so that interaction with specific wavelengths of light can be measured to classify reactions in the sensor.
Claim 5: Campanella-Pineda and Veiseh disclose the structure according to claim 1 (as discussed above).
Neither Campanella-Pineda nor Veiseh appear to disclose the ISFET includes a drain region, a source region, and a channel region, and wherein the cavity extends to a bottom surface of the drain region, the source region, and the channel region of the ISFET.
However, Wolf teaches the ISFET (Fig 5. col 5 lines 12-15 “in the example of a planar sensor #5 integrated into the substrate of the semiconductor chip #3 and constructed as a field-effect transistor”) includes -a drain region, a source region, and a channel region (Fig 5. field-effect transistor has three main terminals gate, source, and drain), and wherein the cavity extends to a bottom surface of the drain region, the source region, and the channel region of the ISFET ( Fig 5, col 5 lines 15-16 “the cells #6 are arranged directly adjacent to the planar sensors #5”).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Wolf with Campanella-Pineda and Veiseh to implement the ISFET includes a drain region, a source region, and a channel region, and wherein the cavity extends to a bottom surface of the drain region, the source region, and the channel region of the ISFET because this connectivity enhances the surface area of the device exposed to the analyte and potentially increases the sensitivity of the ISFET.
Claim 6: Campanella-Pineda and Veiseh disclose the structure according to claim 1 (as discussed above).
Neither Campanella-Pineda nor Veiseh appear to disclose the cavity further includes, within the semiconductor substrate, at least one inlet and at least one outlet for passing a sample into and out of the cavity.
However, Wolf teaches the cavity further includes, within the semiconductor substrate ( Col. 6 lines 30 - 36 an optical window #15, which is inserted into a hole in the substrate of the semiconductor chip #3. The inner side of the window #15 facing the test chamber #2 forms a plane with the active inner side of the semiconductor chip #3, on which the biological cells #6 are adherently deposited), at least one inlet and at least one outlet for passing a sample into and out of the cavity (Figs 1 and 2, col 5, lines 51-53, “the seal #7 is constructed as a silicone seal, which is penetrated by an inlet channel #10 and an outlet channel #11”).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Wolf with Campanella-Pineda and Veiseh to implement the cavity further includes, within the semiconductor substrate, at least one inlet and at least one outlet for passing a sample into and out of the cavity because the inlets and outlets enable controlled flow of fluids within the microchannels of the device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Campanella-Pineda et al.; US 2021/0010971 A1; 07/2019 in view of Veiseh et al.; US 2020/0101455 A1; 10/2019 and Wolf et al.; US 6,277,629 B1; 06/2000 as applied to claim 5 above, and further in view of Smith et al.; US 4,874,499 ; 05/1988.
Claim 7: Campanella-Pineda, Veiseh, and Wolf disclose the structure according to claim 5 (as discussed above).
Neither Campanella-Pineda nor Veiseh nor Wolf appear to disclose the ISFET further includes a gate electrode adjacent the channel region opposite the cavity further comprising an insulating layer on the substrate, and a device layer on the insulating layer, wherein the cavity extends through the substrate and the insulating layer to a bottom surface of the device layer, and wherein the opening extends through the device layer to the cavity.
However, Smith teaches the ISFET further includes a gate electrode ( Fig. 3A electrode #36, Col. 9 lines 50 – 52 An Ag/AgCL electrode #36 is provided over the FETS #38 in the underlying silicon substrate #40) adjacent the channel region opposite the cavity further comprising an insulating layer on the substrate (col 7, lines 18-23 “Many of the solid state materials, such as silicon nitride and aluminum oxide, which are used as hydrogen ion sensitive membranes are also insulators and excellent diffusion barriers to water and ions. They are often incorporated as the upper most layer of the FET gate insulator and as an encapsulant”), and a device layer on the insulating layer (Fig. 3 col 9, lines 39-40 “a reference FET which incorporates a porous membrane”), wherein the cavity extends through the substrate (Fig 3A, col 9, lines 47-48, “fill channels 26 extending into the cavity 28”) and the insulating layer to a bottom surface of the device layer ( col 9. lines 53-54, “the structure 30 is adhered to the substrate 40”), and wherein the opening extends through the device layer to the cavity (see Fig. 3a and 3b).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Smith with Campanella-Pineda, Veiseh, and Wolf to implement the ISFET further includes a gate electrode adjacent the channel region opposite the cavity further comprising an insulating layer on the substrate, and a device layer on the insulating layer, wherein the cavity extends through the substrate and the insulating layer to a bottom surface of the device layer, and wherein the opening extends through the device layer to the cavity because the separate gate electrode acts as the transducer, converting the charges at the sensing cavity into an electrical signal that can easily be measured and processed.
Response to Arguments
Applicant's arguments filed 12/16/2025 have been fully considered but they are not persuasive. With regard to the Claim 1 argument, MPEP 2145 III states “In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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