DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 10/23/2025. Claims 1-27 are pending in this application. Claims 1 and 13 are amended. Claims 19-27 remain withdrawn.
Claims 1-18 are presented in this Office Action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US 2023/0005962; hereinafter ‘Lee’).
Regarding claim 13, Lee teaches a display device (100, FIG. 3, [0052]) comprising:
a substrate (110 includes 111 and 112, FIG. 1, [0043, 0052]; hereinafter ‘SUB’) comprising a display area (a region in which 130 and 120 are disposed; hereinafter ‘DA’) in which pixels (P) are located (shown in FIG. 1), a pad area (A, FIGS. 1 and 2) at one side of the display area (A at the one side of DA, as illustrated by opposite sides of a cross-section taken along line III-III’, FIGS. 1-3), and an inclined area (a region adjacent to the leftmost side surface of 100; hereinafter ‘IA’) on one side of the pad area (the left side of A);
a passivation layer (119 and 170 includes 171 and 172, [0069, 0095]; hereinafter ‘PL’) covering the display area (DA) and the pad area (A) of the substrate (SUB);
a via layer (113, 114, 115, and 116, [0056-0058, 0065]; hereinafter ‘VL’) between the substrate (SUB) and the passivation layer (PL) in the display area (DA); and
a pad (180T2, [0074]) between the substrate (SUB) and the passivation layer (PL) in a thickness direction (shown in FIG. 3) in the pad area (A) to overlap the substrate (SUB) and the passivation (PL) in plan view (although illustrated in cross-section in FIG. 3, the overlap in plan view is understand by projecting the illustrated structure along a thickness direction),
wherein the passivation layer (PL) defines:
a first exposure opening (the opening located between 172 and the second 119 from the left above 106; hereinafter ‘VLO1’) adjacent a boundary (a boundary) between the display area (DA) and the pad area (A) in the display area (DA), and exposing the via layer (VL); and
a second exposure opening (the opening located between a leftmost 119 and 172 above 180T2; hereinafter ‘VLO2’) in the pad area (A) and exposing the pad (180T2).
Regarding claim 14, Lee teaches the display device of claim 13, further comprising a side wiring (152, FIG. 3, [0074]) in the pad area (A) and in the inclined area (IA), and electrically connected to the pad (180T2) through the second exposure opening (VLO2).
Regarding claim 15, Lee teaches the display device of claim 14, wherein the side wiring (152, FIG. 3, [0074]) is spaced from the first exposure opening (VLO1).
Regarding claim 16, Lee teaches the display device of claim 15, further comprising side wirings (150 includes 151 and 152, FIGS. 2 and 3, [0051, 0073]), which comprise the side wiring (152), that are spaced from each other in a first direction (a first direction extending along an arrangement direction of 150; hereinafter ‘F1’), and wherein the first exposure opening (VLO1) extends in the first direction (F1, since FIG. 3 illustrates that VLO1 and 150 are intersected by the same cross-sectional plane, indicating that each has an extend along a direction orthogonal to the cross-sectional plane) to correspond to the side wirings (150).
Regarding claim 17, Lee teaches the display device of claim 16, wherein the pixels (P, FIG. 1) comprises an outermost pixel (the portion of the outmost P of DA adjacent to the cross-sectional line III-III’ on an outward side III, FIG. 3; hereinafter ‘OP’) adjacent to the pad area (PA), wherein the passivation layer (PL) further defines a third exposure opening (the left side opening of 171 above 180T1, [0074]; hereinafter ‘VLO3’) adjacent to the outermost pixel (OP), and spaced from the first exposure opening (VLO1) with the outermost pixel (OP) interposed therebetween (shown in FIG. 3).
Regarding claim 18, Lee teaches the display device of claim 15, further comprising side wirings (150 includes 151 and 152, FIGS. 2 and 3, [0051, 0073]), which comprise the side wiring (152), that are spaced from each other in a first direction (a first direction extending along an arrangement direction of 150; hereinafter ‘F1’), wherein the passivation layer (PL) further defines first exposure openings (VLO1 for 131G and 131B), which comprise the first exposure opening (VLO1 for 131R), that are spaced from each other in the first direction (F1, shown in FIGS. 1 and 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2020/0203235; hereinafter ‘Jung’) in view of Shin et al. (US 2020/0235128; hereinafter ‘Shin’).
Regarding claim 1, Jung teaches a display device (FIG. 3C, [0054]) comprising:
a substrate (50, [0058]) comprising a first surface (50a, FIG. 2), a second surface (50b, FIG. 4B, [0171]) opposite to the first surface (50a), a first chamfered surface (CF1, [0225]) extending from one side of the first surface (50a), a second chamfered surface (CF2) extending from one side of the second surface (50b), and a first side surface(50-1, [0087]) connecting the first chamfered surface (CF1) and the second chamfered surface to each other (CF2);
a first pad (20, [0058]) on the first surface (50a);
an upper via layer (81, [0070]) on the first surface (50a) and spaced from the first pad (20) in plan view (although shown in cross-sectional view in FIG. 3C, in plan view, 81 is laterally spaced apart from 20) to not overlap the first pad (20) in a thickness direction (shown in FIG. 3C); and
a first passivation layer (an insulating layer disposed above 61, [0114, 207-208]; hereinafter referred to as ‘PL1’) partially covering the upper via layer (PL1 partially covering 81), and defining a first exposure opening (opening of 81 that is not covered by PL1; hereinafter referred to ‘81O’) exposing one side of the upper via layer facing the first pad (81O exposing the left side of 81 facing 20).
Jung does not teach the display device comprising an upper via layer comprising electrically insulative material.
Shin teaches a display device (1. FIGS. 1 and 2, [0053, 0055]) comprising an upper via layer (a via layer including 50, 51, 150, and 236, FIG. 15, [0249, 0254-0255]; hereinafter ‘UVLShin’), comprising electrically insulative material (150 including SiO2, SiN, or Al2O3, [0097]).
As taught by Shin, one of ordinary skill in the art would utilize and modify the above teaching into Jung to obtain and achieve the display device comprising an upper via layer comprising electrically insulative material as claimed, because the insulative material is formed to cover the metal portions to provide isolation and protection of the via structure [0095-0097).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shin in combination with Jung due to above reason.
Regarding claim 2, Jung in view of Shin teaches the display device of claim 1, further comprising:
a second pad (Jung: 110, FIG. 4B, [0160]) on the second surface (110 on 50b); and
a side wiring (100) on the first surface (100 on 50-1), on the first chamfered surface, on the first side surface, and on the second chamfered surface (100 on 50a, CF1, 50-1, and CF2), and electrically connecting the first pad and the second pad to each other (20 and 110 are electrically connected, [0160]).
Regarding claim 3, Jung in view of Shin teaches the display device of claim 2, further comprising
an interlayer insulating layer (Jung: 61, FIG. 4B, [0114]) between the first pad and the substrate, and between the upper via layer and the substrate (61 between 20 and 50, and 81 and 50),
wherein the side wiring (100) is in direct contact with the interlayer insulating layer in an area between the first pad and the upper via layer (100 is in direct contact with 61 in the area between 20 and 81).
Regarding claim 4, Jung in view of Shin teaches the display device of claim 3, wherein the side wiring is spaced from the one side of the upper via layer facing the first pad (Jung: 100 is spaced from the left side of 81 facing 20, FIG. 4B).
Regarding claim 9, Jung in view of Shin teaches the display device of claim 1, Jung does not teach the display device wherein the upper via layer comprises a first via layer on the substrate, a second via layer on the first via layer, and a third via layer on the second via layer, and wherein the display device further comprises: a thin film transistor between the first via layer and the substrate; and a light emitting element on the third via layer, and electrically connected to the thin film transistor.
Shin teaches the display device
wherein the upper via layer (UVLShin, FIG. 15) comprises a first via layer (236) on the substrate (21), a second via layer (50) on the first via layer (236), and a third via layer (51) on the second via layer (50), and
wherein the display device further comprises:
a thin film transistor (23), between the first via layer (236) and the substrate (21); and
a light emitting element (121, FIG. 12B, [0205]) on the third via layer (51, not explicitly shown in FIG. 12B, but inherently includes as a capping layer 51 on the metal via layer 50, [0249]), and electrically connected to the thin film transistor (23, see [0072-0073]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Shin to obtain and achieve the display device wherein the upper via layer comprises a first via layer on the substrate, a second via layer on the first via layer, and a third via layer on the second via layer, and wherein the display device further comprises: a thin film transistor between the first via layer and the substrate; and a light emitting element on the third via layer, and electrically connected to the thin film transistor as claimed, because a multi-layer via structure provides reliable vertical electrical interconnection and protection of underlying layers while maintaining process compatibility [0220, 0225, 0235].
Regarding claim 10, Jung in view of Shin teaches the display device of claim 9, wherein the one side of the upper via layer facing the first pad and exposed by the first exposure opening (Jung: the left side of 81 facing 20 and exposed by 81O, FIG. 3C).
Jung does not teach the display device wherein the one side of the upper via layer comprises at least one of one side of the first via layer facing the first pad, one side of the second via layer facing the first pad, or one side of the third via layer facing the first pad.
Shin teaches the display device wherein the one side of the upper via layer (the left side of UVLShin, FIG. 13) facing the first pad (the leftmost 232, [0222]; hereinafter ‘L232’) and exposed by the first exposure opening (the opening of UVLShin that is not covered by 253, [0248]; hereinafter referred to ‘253O’) comprises at least one of one side of the first via layer facing the first pad, one side of the second via layer facing the first pad, or one side of the third via layer facing the first pad (the left side of 50 and 51 facing L232).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Shin to obtain and achieve the display device wherein the one side of the upper via layer comprises at least one of one side of the first via layer facing the first pad, one side of the second via layer facing the first pad, or one side of the third via layer facing the first pad as claimed, because at lease a portion of the multi-layer via structure is exposed above the insulating layer to serve as an electrical contact to an overlying light emitting element [0234-0235].
Regarding claim 12, Jung in view of Shin teaches the display device of claim 9, wherein the light emitting element is a flip chip-type micro light emitting diode element (Jung: 90 on 81 is a flip chip, FIG. 3C, [0170]).
Claims 5-8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 2020/0203235) in view of Shin (US 2020/0235128), and further in view of Lee (US 2023/0005962).
Regarding claim 5, Jung in view of Shin teaches the display device of claim 4, but does not teach the display device further comprising an overcoat layer covering the side wiring, and in direct contact with the one side of the upper via layer facing the first pad.
Lee teaches a display device (100, FIG. 3, [0052]) further comprising an overcoat layer (172, [0095]) covering the side wiring (152, [0074]), and in direct contact with the one side of the upper via layer facing the first pad (172 in direct contact with the left side of 116 facing the 180T1, [0065, 0072]).
As taught by Lee, one of ordinary skill in the art would utilize and modify the above teaching into Jung in view of Shin to obtain and achieve the display device further comprising an overcoat layer covering the side wiring, and in direct contact with the one side of the upper via layer facing the first pad as claimed, because the outer side of the via layers is covered to prevent physical and chemical degradation, whereas the inner side is intentionally left exposed to allow subsequent bonding and electrical interconnection processes [0004, 0011].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination with Jung in view of Shin due to above reason.
Regarding claim 6, Jung in view of Shin and Lee teaches the display device of claim 5, further comprising a lower via layer (Jung: 320, FIG. 11, [0217]) on the second pad (340), and a second passivation layer (341) partially covering the lower via layer (341 partially covering 320),
wherein the second pad is closer to the second chamfered surface than the lower via layer (340 is closer to CF2 than 320), and
wherein the second passivation layer defines a second exposure opening (opening of 320 that is not covered by 341; hereinafter referred to ‘320O’) exposing one side of the lower via layer adjacent to the second chamfered surface (320O exposing the left side of 320 adjacent to CF2).
Regarding claim 7, Jung in view of Shin and Lee teaches the display device of claim 6, wherein the side wiring (Jung: 280, FIG. 11, [0226]) is spaced from the one side of the lower via layer adjacent to the second chamfered surface (280 is spaced from the left side of 320 adjacent to CF2).
Regarding claim 8, Jung in view of Shin and Lee teaches the display device of claim 7, but does not teach the display device wherein the overcoat layer is in direct contact with the one side of the lower via layer adjacent to the second chamfered surface.
Lee, however, teaches that the overcoat layer (171, [0051]) in direct contact with the one side of the lower via layer adjacent to the outer side surface (171 in direct contact with the left side of 180B2, [0082]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Lee to implement the overcoat layer is in direct contact with the one side of the via layer adjacent to the second chamfered surface as claimed, because the outer side of the conductive features is covered to prevent physical and chemical degradation [0004, 0011].
Regarding claim 11, Jung in view of Shin teaches the display device of claim 10, further comprising light emitting elements (Jung: a plurality of 90, FIG. 4A, [0059]), which comprise the light emitting element, that are spaced from each other (the 90s are spaced from each other).
Jung in view of Shin does not teach the display device wherein the upper via layer further comprises fourth via layers between the light emitting elements, on the third via layer, and comprising an outermost fourth via layer adjacent to the first pad, and wherein the first passivation layer defines a second exposure opening exposing one side of the outermost fourth via layer adjacent to the first pad.
Lee teaches a display device (100, FIG. 3, [0052])
wherein the upper via layer (113, 114, and 115, [0056-0058]) further comprises fourth via layers (116, [0065]) between the light emitting elements (116 between 130, FIG. 1), on the third via layer (116 on 115), and comprising an outermost fourth via layer adjacent to the first pad (the outmost 116 adjacent to 180T2, [0072]), and
wherein the first passivation layer (119, [0069]) defines a second exposure opening (opening of 116 over 120 that is not covered by 119; hereinafter referred to as ‘116O’) exposing one side of the outermost fourth via layer adjacent to the first pad (116O exposing the one side of 116 adjacent to 180T2).
As taught by Lee, one of ordinary skill in the art would utilize and modify the above teaching into Jung in view of Shin to obtain and achieve the display device wherein the upper via layer further comprises fourth via layers between the light emitting elements, on the third via layer, and comprising an outermost fourth via layer adjacent to the first pad, and wherein the first passivation layer defines a second exposure opening exposing one side of the outermost fourth via layer adjacent to the first pad as claimed, because the region between the light emitting elements is planarized in order to reduce interlayer step differences during subsequent processes [0065] and the outer side of the via layers is covered to prevent physical and chemical degradation, whereas the inner side is intentionally left exposed to allow subsequent bonding and electrical interconnection processes [0004, 0011].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination with Jung in view of Shin due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits, in page 14 of Remark, that “Accordingly, Jung and Lee do not appear to disclose the amended features of claims 1 and 13.”.
The examiner respectfully disagrees.
With respect to claim 1, the newly added limitation of “an upper via layer comprising electrically insulative material on the first surface and spaced from the first pad in plan view to not overlap the first pad in a thickness direction” is taught by Shin. Accordingly, a new ground of rejection has been made as set forth above.
With respect to claim 13, the newly added limitation of “a pad between the substrate and the passivation layer in a thickness direction in the pad area to overlap the substrate and the passivation layer in plan view” is also met by the applied prior art when the term “passivation layer” is reasonably interpreted in light of Applicant’s disclosure.
Specifically, Applicant does not define the passivation layer by a particular material or as a single discrete layer, but instead describes the passivation layer primarily in term of its relative position and function. Consistent with this broad disclosure, the passivation layer reasonably encompasses the combined structure including layers 170 (insulating layer) and 119 (bank layer). Under this interpretation, the pad is disposed between the substrate and the passivation layer in the thickness direction and overlaps the substrate and the passivation layer in plan view, as required by amended claim 13. Hence, under BRI, given a broadest reasonable interpretation, Lee teaches the claimed features.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/18/26