Prosecution Insights
Last updated: April 19, 2026
Application No. 18/051,668

DISPLAY DEVICE

Final Rejection §102
Filed
Nov 01, 2022
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
283 granted / 371 resolved
+8.3% vs TC avg
Strong +23% interview lift
Without
With
+23.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
31 currently pending
Career history
402
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 371 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 8-9, 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0061948 A1 (Park). Re claim 1, Park teaches a display device (organic light emitting diode display [0035] Fig. 2) comprising: a substrate (substrate 101); a transistor on the substrate (thin film transistor formed of elements 102/104/106/108); a first electrode (first electrode 108-2) connected to the transistor; a first passivation layer (first planarization layer 107-1) between the transistor and the first electrode; a wire (112) on the first passivation layer, overlapping the first electrode, comprising a first portion (portion of 112 connecting to layer 114) and a second portion having a greater width than the first portion in a plan view (portion of 122 that is patterned to form second outgassing patterns see annotated Fig. 3A below and while the device is seen in cross section view, the relative dimensions of the portions would be the same when viewed from plan view) and defining an opening pattern (second out gassing patterns) at the second portion; and a second passivation layer (first planarization layer 107-2) between the wire and the first electrode. PNG media_image1.png 828 989 media_image1.png Greyscale PNG media_image2.png 471 730 media_image2.png Greyscale Re claim 2, Park teaches wherein the first passivation layer comprises an organic insulating material ([0041]). Re claim 3, Park teaches wherein the second passivation layer comprises an organic insulating material ([0041]). Re claim 4, Park teaches wherein the opening pattern of the wire overlaps the first electrode (Fig. 2). Re claim 8, Park teaches wherein the wire overlaps a region between a center portion of the first electrode and an edge on one side of the first electrode (Fig. 2). Re claim 9, Park teaches wherein the wire is adjacent an edge on one side of the first electrode (Fig. 2). Re claim 17, Park teaches a connection electrode for connecting the transistor to the first electrode, and at a same layer as the wire (electrode 108-2 in direct contact with drain 108). Re claim 18, Park teaches wherein the wire is connected to the transistor and is configured to receive a voltage ([0051-0055]). Re claim 19, Park teaches wherein the wire comprises: a data line for applying a data signal; or a driving voltage line for applying a driving voltage, having a width that is greater than that of the data line, and having the opening pattern formed therein (108-2 connected to the driving transistor and [0041] states that the various 108-2 layers serve as signal lines/electrodes and have openings which expose the underlying planarization layer Fig. 4B). PNG media_image3.png 529 507 media_image3.png Greyscale Response to Arguments Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on the reference as it is being applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Nov 01, 2022
Application Filed
Oct 06, 2025
Non-Final Rejection — §102
Dec 31, 2025
Response Filed
Mar 10, 2026
Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+23.4%)
2y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 371 resolved cases by this examiner. Grant probability derived from career allow rate.

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