DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/8/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-9, 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0061918 A1 (Park).
Re claim 1, Park teaches a display device (organic light emitting diode display [0035] Fig. 2) comprising:
a substrate (substrate 101);
a transistor on the substrate (thin film transistor formed of elements 102/104/106/108);
a first electrode (first electrode 112) connected to the transistor;
a first passivation layer (first planarization layer 107-1) between the transistor and the first electrode;
a wire (metal layers 108-2 in annotated Fig. 2 below) between the first passivation layer and the first electrode, overlapping the first electrode, comprising a first portion (narrower portions on the right) and a second portion having a greater width (wider portion of the left) than the first portion in a plan view and defining an opening pattern (spaces between) at the second portion and overlapping the first electrode (overlap in the direction normal to the surface of the substrate); and
a second passivation layer (first planarization layer 107-2) between the wire and the first electrode.
[AltContent: rect]
PNG
media_image1.png
828
989
media_image1.png
Greyscale
Re claim 2, Park teaches wherein the first passivation layer comprises an organic insulating material ([0041]).
Re claim 3, Park teaches wherein the second passivation layer comprises an organic insulating material ([0041]).
Re claim 4, Park teaches wherein the opening pattern of the wire overlaps the first electrode (Fig. 2).
Re claim 8, Park teaches wherein the wire overlaps a region between a center portion of the first electrode and an edge on one side of the first electrode (Fig. 2).
Re claim 9, Park teaches wherein the wire is adjacent an edge on one side of the first electrode (Fig. 2).
Re claim 17, Park teaches a connection electrode for connecting the transistor to the first electrode, and at a same layer as the wire (electrode 108-2 in direct contact with drain 108).
[AltContent: rect]
PNG
media_image1.png
828
989
media_image1.png
Greyscale
Re claim 18, Park teaches wherein the wire is connected to the transistor and is configured to receive a voltage ([0051-0055]).
Re claim 19, Park teaches wherein the wire comprises: a data line for applying a data signal; or a driving voltage line for applying a driving voltage, having a width that is greater than that of the data line, and having the opening pattern formed therein (108-2 connected to the driving transistor and [0041] states that the various 108-2 layers serve as signal lines/electrodes and have openings which expose the underlying planarization layer Fig. 4B).
PNG
media_image2.png
529
507
media_image2.png
Greyscale
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on the reference as it is being applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Prosecution Insights