9DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Group I (claims 1-17) in the reply filed on October 29th, 2025 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Objections
Claims 4 and 13 are objected to because of the following informalities:
Claim 4 recites “the at least one of the gate subset” in lines 4-5 referring back to “at least one of the gate subset of the first array” in lines 1-2 and should be amended to “the at least one of the gate subset of the first array” for avoiding confusion. Appropriate correction is required.
Claim 13 recites “the at least one of the gate subset” in lines 4-5 referring back to “at least one of the gate subset of the first array” in lines 1-2 and should be amended to “the at least one of the gate subset of the first array” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 3 recites “a gate runner disposed in the first metal layer and separated from the gate pad metal, and connected to the gate pad metal by the gate subset of the first array and the gate subset of the second array in lines 3-6. Claims 1 and 3 recites the semiconductor device having all of the gate pad metal and the gate runner disposed in the same metal layer of the first metal layer above the layer of the gate subset of the first array and the gate subset of the second array. It is unclear to the examiner how can the gate runner connected to the gate pad metal by the gate subset of the first array and the gate subset of the second array when they are located in the layer below the gate runner and the gate pad metal.
Claim 12 recites “a gate runner disposed in the first metal layer and separated from the gate pad metal, and connected to the gate pad metal by the gate subset of the first array and the gate subset of the second array in lines 2-4. Claims 10 and 12 recites the semiconductor device having all of the gate pad metal and the gate runner disposed in the same metal layer of the first metal layer above the layer of the gate subset of the first array and the gate subset of the second array. It is unclear to the examiner how can the gate runner connected to the gate pad metal by the gate subset of the first array and the gate subset of the second array when they are located in the layer below the gate runner and the gate pad metal.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-11, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MATSUSHITA et al. (Pub. No.: US 2017/0271451 A1), hereinafter as Matsushita.
Regarding claim 1, Matsushita discloses a semiconductor device in Figs. 21-23B, comprising: a plurality of transistors (a plurality of IGBTs) including a plurality of source regions (plurality of regions 5) and a plurality of gate electrodes (plurality of gate electrodes 20) (see Figs. 22-23A and [0255], [0257]); a first dielectric layer (insulation layer 61) formed on the plurality of source regions and the plurality of gate electrodes (see Figs. 23A-23B and [0068-0069], [0253]); a first array of low-resistance material (array of plugs 55 and plugs 57a being tungsten) formed in the first dielectric layer, with a gate subset of the first array (plurality of plugs 55) formed on the plurality of gate electrodes (gate electrodes 20) and a source subset of the first array (plurality of plugs 57a) formed on the plurality of source regions (regions 5) (see Figs. 23A-23B and [0256-0257], [0283]); a second dielectric layer (insulation layer 62) formed on the first dielectric layer and on the first array (see Figs. 23A-23B and [0253]); a second array of low-resistance material (array of plugs 56 and 57b being tungsten) formed in the second dielectric layer, with a gate subset of the second array (plurality of plugs 56) formed on the gate subset of the first array (indirectly on plurality of plugs 55 through metal layers 42) and thereby electrically connected to the plurality of gate electrodes (see Figs. 22, 23A-23B and [0258]), and a source subset of the second array (plurality of plugs 57b) formed on the source subset of the first array (plurality of plugs 57a) and thereby electrically connected to the plurality of source regions (see Fig. 23A and [0257]); a gate pad metal (gate wiring 33) formed on the second dielectric layer and electrically connected to the gate subset of the second array (plurality of plugs 56) (see Figs. 21, 23B and [0086], [0253]); and a source pad metal (source pad 32) formed on the second dielectric layer and electrically connected to the source subset of the second array (plurality of plugs 57a) (see Figs. 21, 23B and [0086], [0257], [0260]).
Regarding claim 2, Matsushita discloses the semiconductor device of claim 1, wherein the first array and the second array are linear arrays (see Figs. 23A-23B), and the gate subset of the first array and the source subset of the first array (array of plugs 55 and 57a) are parallel to one another (see Fig. 23A), with the gate subset of the second array landed on the gate subset of the first array (plurality of plugs 56 landed indirectly on plurality of plugs 55), and the source subset of the second array landed on the source subset of the first array (plurality of plugs 57b landed on plurality of plugs 57a) (see Figs. 23A-23B).
Regarding claim 6, Matsushita discloses the semiconductor device of claim 1, wherein: the first array and the second array include tungsten (see [0283]); and the plurality of gate electrodes includes doped polysilicon (see [0084]).
Regarding claim 7, Matsushita discloses the semiconductor device of claim 1, wherein the plurality of transistors are included in a silicon carbide (SiC) semiconductor region (see [0083]).
Regarding claim 8, Matsushita discloses the semiconductor device of claim 7, wherein: the plurality of transistors includes vertical field-effect transistors (FETs) (including regions 2, 3, 4, 5, gate 20, drain electrode 31, plug 57a), and the SiC semiconductor region includes a drift region of the vertical FETs (region 3) and a drain region of the vertical FETs (region 2) (see Fig. 23A and [0229], [0291]).
Regarding claim 9, Matsushita discloses the semiconductor device of claim 7, wherein: the plurality of transistors includes a vertical insulated gate bipolar transistor (IGBT) (see [0291]), with the plurality of source regions including emitter regions (regions 5 being emitters) of the vertical IGBT, and the SiC semiconductor region including a drift region of the vertical IGBT (region 3) and a collector region of the vertical IGBT (region 2) (see [0291]).
Regarding claim 10, Matsushita discloses a semiconductor device in Figs. 21-23B, comprising: a plurality of transistors (a plurality of IGBTs) including a plurality of source regions (plurality of regions 5) and a plurality of gate electrodes (plurality of gate electrodes 20) (see Figs. 22-23A and [0255], [0257]); a first array of low-resistance material (array of plugs 55 and plugs 57a being tungsten) formed at a first plug layer (the plug layer in insulating layer 61) on the plurality of transistor, with a gate subset of the first array (plurality of plugs 55) formed on the plurality of gate electrodes (gate electrodes 20) and a source subset of the first array (plurality of plugs 57a) formed on the plurality of source regions (regions 5) (see Figs. 23A-23B and [0253], [0256-0257], [0283]); a second array of low-resistance material (array of plugs 56 and 57b being tungsten) formed at a second plug layer (the plug layer in insulating layer 62) on the first plug layer, with a gate subset of the second array (plurality of plugs 56) formed on the gate subset of the first array (indirectly on plurality of plugs 55 through metal layers 42) and thereby electrically connected to the plurality of gate electrodes (see Figs. 22, 23A-23B and [0253], [0258]), and a source subset of the second array (plurality of plugs 57b) formed on the source subset of the first array (plurality of plugs 57a) and thereby electrically connected to the plurality of source regions (see Fig. 23A and [0257]); a gate pad metal (gate wiring 33) formed at a first metal layer (metal layer above insulating layer 62) on the second plug layer and electrically connected to the gate subset of the second array (plurality of plugs 56) (see Figs. 21, 23B and [0086], [0253]); and a source pad metal (source pad 32) formed at the first metal layer and electrically connected to the source subset of the second array (plurality of plugs 57a) (see Figs. 21, 23B and [0086], [0257], [0260]).
Regarding claim 11, Matsushita discloses the semiconductor device of claim 10, wherein the first array and the second array are linear arrays (see Figs. 23A-23B), and the gate subset of the first array and the source subset of the first array (array of plugs 55 and 57a) are parallel to one another (see Fig. 23A), with the gate subset of the second array landed on the gate subset of the first array (plurality of plugs 56 landed indirectly on plurality of plugs 55), and the source subset of the second array landed on the source subset of the first array (plurality of plugs 57b landed on plurality of plugs 57a) (see Figs. 23A-23B).
Regarding claim 15, Matsushita discloses the semiconductor device of claim 10, wherein: the first array and the second array include tungsten (see [0283]); and the plurality of gate electrodes includes doped polysilicon (see [0084]).
Regarding claim 16, Matsushita discloses the semiconductor device of claim 10, wherein the plurality of transistors are included in a silicon carbide (SiC) semiconductor region (see [0083]).
Regarding claim 17, Matsushita discloses a method of making a semiconductor device in Figs. 21-23B, comprising: forming in a substrate (combination of regions 2, 3, 4, and 5), a plurality of transistors (a plurality of IGBTs) including a plurality of source regions (plurality of regions 5) and a plurality of gate electrodes (plurality of gate electrodes 20) (see Figs. 22-23A and [0255], [0257]); forming a first dielectric layer (insulation layer 61) formed on the plurality of source regions and the plurality of gate electrodes (see Figs. 23A-23B and [0068-0069], [0253]); forming a first array of low-resistance material (array of plugs 55 and plugs 57a being tungsten) formed in the first dielectric layer, with a gate subset of the first array (plurality of plugs 55) formed on the plurality of gate electrodes (gate electrodes 20) and a source subset of the first array (plurality of plugs 57a) formed on the plurality of source regions (regions 5) (see Figs. 23A-23B and [0256-0257], [0283]); forming a second dielectric layer (insulation layer 62) formed on the first dielectric layer and on the first array (see Figs. 23A-23B and [0253]); forming a second array of low-resistance material (array of plugs 56 and 57b being tungsten) formed in the second dielectric layer, with a gate subset of the second array (plurality of plugs 56) formed on the gate subset of the first array (indirectly on plurality of plugs 55 through metal layers 42) and thereby electrically connected to the plurality of gate electrodes (see Figs. 22, 23A-23B and [0258]), and a source subset of the second array (plurality of plugs 57b) formed on the source subset of the first array (plurality of plugs 57a) and thereby electrically connected to the plurality of source regions (see Fig. 23A and [0257]); forming a gate pad metal (gate wiring 33) formed on the second dielectric layer and electrically connected to the gate subset of the second array (plurality of plugs 56) (see Figs. 21, 23B and [0086], [0253]); and forming a source pad metal (source pad 32) formed on the second dielectric layer and electrically connected to the source subset of the second array (plurality of plugs 57a) (see Figs. 21, 23B and [0086], [0257], [0260]).
Allowable Subject Matter
Claims 4-5 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if amended or rewritten to overcome the objections of claims 4 and 13 as set forth in the office action above and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: wherein at least one of the gate subset of the first array is slotted above an underlying gate electrode of the plurality of gate electrodes, with the first dielectric layer thereby being in contact with the underlying gate electrode within a slot, so that a gate current through the at least one of the gate subset is directed through the underlying gate electrode under the slot during operation of the semiconductor device as in claims 4 and 13. Claims 5 and 14 depend on claims 4 and 13, and therefore also include said claimed limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818