DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on May 12, 2026 has been entered. No claim(s) has/have been canceled or added. Therefore, claim(s) 1-24 remain(s) pending in the application with claims 5-6, 8, 10, 18-19, 21 and 23 withdrawn from consideration.
Claim Objections
Claim(s) 15-23 is/are objected to because of the following informalities:
With respect to claim 15, as currently amended the claim requires coupling a first baseplate or a second plate to the substrate and “including a first pin fin” and “including a second pin fin”. It is suggested that the language be modified to specify that it is the first baseplate and the second baseplate that include the first pin fin and the second pin fin, respectively. Claims 16-23 which either directly or indirectly depend form claim 15 and which include issues of claim 15 are objected to for similar reasons.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-4, 7, 9 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, as currently presented the claim requires “a first power electronic module covering the at least one opening in the first sidewall with a surface of a substrate in the first power electronic module” and “a second power electronics module covering the at least one opening in the second sidewall with a surface of a substrate in the second power electronics module”. It is unclear from the claim language, however, if it is a surface of a substrate of the first power electronics module and the second power electronics module, respectively, that are covering that at least one opening in the first sidewall and the at least one opening in the second sidewall, or some other parts of the first and second power electronics module are covering the at least one opening in the first sidewall and the at least one opening in the second sidewall or if the first sidewall and the second sidewall include a surface of a substrate. For purpose of compact prosecution, it will be assumed that the first and the second power electronics modules each include a substrate, where a surface of the substrate of the first power electronics module covers the at least one opening in the first sidewall and a surface of the substrate of the second power electronics module covers the at least one opening in the second sidewall. Claims 2-4, 7, and 9 which either directly or indirectly depends from claim 1 and which inherit issues of claim 1 are rejected for similar reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 9, 11-17, 20, 22 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Rinehart et al. (US 7,197,819, hereinafter “Rinehart”, previously cited) in view of Ushijima et al. (US 2016/0104654, hereinafter “Ushijima”, previously cited).
Regarding claim 1, Rinehart teaches in Fig. 1-5 (Figs. 1 and 5 shown below) and related text a package comprising:
a frame (12, Fig. 1 and col. 2, ll. 50-64) having a first sidewall and a second sidewall opposite the first sidewall, the frame having at least one opening (16, Fig. 1 and col. 2, ll. 50-64) in the first sidewall and at least one opening (16, Fig. 1 and col. 2, ll. 50-64) in the second sidewall ;
a first power electronics module (14 or 50, Figs. 1, 4A-4B, 5, col. 2, ll. 50-64, col. 3, ll. 54-67 and col. 4, ll. 1-2) covering the at least one opening in the first sidewall (Figs. 1 and 5) with a surface of a substrate (32, Fig. 2 and col. 3, ll. 11-20) in the first power electronics module;
a first baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) coupled to the substrate (32, Fig. 2) of the first electronic module and including a first pin fin (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67);
a second power electronics module (14 or 50, Figs. 1, 4A-4B, 5, col. 2, ll. 50-64, col. 3, ll. 54-67 and col. 4, ll. 1-2) covering the at least one opening in the second sidewall (Figs. 1 and 5) with a surface of a substrate (32, Fig. 2 and col. 3, ll. 11-20) in the second power electronics module (Figs. 1 and 5); and
a second baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) coupled to the substrate (32, Fig. 2) of the second power electronic module and including a second pin fin (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67),
the first sidewall, the surface of the substrate of the first power electronics module, the second sidewall, and the surface of the substrate of the second power electronics module collectively defining a cooling fluid channel (20, Figs. 1, 5 and col. 2, ll. 50-64) through the frame.
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Rinehart, however, does not explicitly teach that the second pin fin is in contact with the first pin fin.
Ushijima, in a similar field of endeavor, teaches in Fig. 14 and related text, a first baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a first semiconductor module (122, Fig. 14 and ¶[0057]) that includes a first pin fin (30, Fig. 14 and ¶[0031]) and second baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a second semiconductor module (124, Fig. 14 and ¶[0057]) that includes a second pin fin (30, Fig. 14 and ¶[0031]), wherein the second pin fin is in contact with the first fin pin in order to inhibit variation in the flow velocity distribution in the cooling medium passage (¶[0063]).
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art to include the second pin fin that is in contact with the first pin fin, as disclosed by Ushijima, in the package disclosed by Rinehart, in order to inhibit variation in the flow velocity distribution in the cooling medium passage.
Regarding claim 2 (1), the combined teaching of Rinehart and Ushijima discloses wherein the surface of the substrate (Rinehart, 32, Figs. 1-2 and col. 3, ll. 11-20) in the first power electronics module is a first surface of the substrate, and the first power electronics module is a single side direct cooled (SSDC) package including a power semiconductor device (Rinehart,30, Fig. 2 and col. 3, ll. 11-20) mounted on a second surface of the substrate opposite the first surface of the substrate (Rinehart, Figs. 1-2 and 5).
Regarding claim 3 (1), the combined teaching of Rinehart and Ushijima further discloses:
an inlet port (Rinehart, 18, Fig. 1 and col. 2, ll. 50-64) disposed at a first end of the frame (Rinehart, 12, Fig. 1); and
an outlet port (Rinehart, 22, Fig. 1 and col. 2, ll. 50-64) disposed at a second end of the frame (Rinehart, 12, Fig. 1) opposite the first end.
Regarding claim 4 (1), the combined teaching of Rinehart and Ushijima discloses wherein the surface of the substrate in the first power electronics module covering the at least one opening seals the at least one opening in the first sidewall alongside the cooling fluid channel (Rinehart, Figs. 1, 5).
Regarding claim 7 (1), the combined teaching of Rinehart and Ushijima discloses wherein the first baseplate (Rinehart, 44, Fig. 2 or 54, Fig. 4B) is attached to the surface of the substrate (Rinehart, 32, Fig. 2) of the first power electronics module exposed to the cooling fluid channel (Rinehart, 20, Fig. 5) in the frame and the first pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extends from the first baseplate into the cooling fluid channel (Rinehart, Figs. 1 and 5).
Regarding claim 9 (1), the combined teaching of Rinehart and Ushijima discloses wherein the first baseplate and the second baseplate are aligned (Rinehart, Fig. 5) so that a top end surface of the first pin touches a top end surface of the second pin fin (Ushijima, Fig. 14 and ¶[0062]).
Regarding claim 11, Rinehart teaches in Figs. 1-5 (Figs. 1 and 5 shown above) a package comprising:
a frame (12, Figs. 1, 5 and col. 2, ll. 50-64) having a cooling fluid channel (20, Fig. 5 and col. 2, ll. 50-64) therethrough, the cooling fluid channel being formed between a first sidewall and a second sidewall opposite the first sidewall (Figs. 1 and 5), the frame including a first plurality of openings (16, Figs. 1, 5 and col. 2, ll. 50-64) disposed in a first row in the first sidewall alongside the cooling fluid channel and a second plurality (Figs. 1, 5, col. 2, ll. 50-64) of openings disposed in a second row in the second sidewall alongside the cooling fluid channel opposite the first sidewall (Figs. 1 and 5);
a first plurality of power electronics modules (14, Figs. 1, 5 and col. 2, ll. 50-64) disposed alongside the first sidewall over the first plurality of openings in the first sidewall (col. 2, ll. 50-64) with each of the first plurality of openings exposing a surface of a substrate (32, Figs. 1, 2, 5 and col. 3, ll. 11-22) in a corresponding one of the first plurality of power electronics modules to the cooling fluid channel (20, Figs. 1 and 5) in the frame (12, Figs. 1 and 5);
a first baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) coupled to the substrate (32, Fig. 2) of a first module of the first plurality of power electronics modules and including a first pin fin (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67);
a second plurality of power electronics modules (14, Figs. 1, 5 and col. 2, ll. 50-64) disposed alongside the second sidewall over the second plurality of openings in the second sidewall (col. 2, ll. 50-64) with each of the second plurality of openings exposing a surface of a substrate in a corresponding one of the second plurality of power electronics modules to the cooling fluid channel in the frame (20, Figs. 1 and 5); and
a second baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) coupled to the substrate (32, Fig. 2) of a second module of the second plurality of power electronics modules and including a second pin fin (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67).
Rinehart, however, does not explicitly teach that the second pin fin is in contact with the first pin fin.
Ushijima, in a similar field of endeavor, teaches in Fig. 14 and related text, a first baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a first semiconductor module (122, Fig. 14 and ¶[0057]) that includes a first pin fin (30, Fig. 14 and ¶[0031]) and second baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a second semiconductor module (124, Fig. 14 and ¶[0057]) that includes a second pin fin (30, Fig. 14 and ¶[0031]), wherein the second pin fin is in contact with the first fin pin in order to inhibit variation in the flow velocity distribution in the cooling medium passage (¶[0063]).
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art to include the second pin fin that is in contact with the first pin fin, as disclosed by Ushijima, in the package disclosed by Rinehart, in order to inhibit variation in the flow velocity distribution in the cooling medium passage.
Regarding claim 12 (11), the combined teaching of Rinehart and Ushijima discloses wherein the first baseplate (Rinehart, 40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) with the first pin fin (Rinehart, 46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) and the second baseplate (Rinehart, 40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) with the second pin fin are exposed to the cooling fluid channel (Rinehart, 20, Figs. 1 and 5) in the frame (Rinehart, 12, Figs. 1 and 5).
Regarding claim 13 (11), the combined teaching of Rinehart and Ushijima discloses wherein the first plurality of power electronics modules and the second plurality of power electronics modules is a single side direct cooled (SSDC) package including a power semiconductor device (Rinehart, 30, Fig. 2 and col. 3, ll. 11-23) mounted on a surface of the substrate (Rinehart, 32, Fig. 2) opposite the surface of the substrate exposed to the cooling fluid channel in the frame (Rinehart, Figs. 1-2 and 5).
Regarding claim 14 (11), the combined teaching of Rinehart and Ushijima discloses wherein the first plurality of power electronics modules and the second plurality of power electronics modules include three single side direct cooled (SSDC) packages (Rinehart, Figs. 1 and 5).
Regarding claim 15, Rinehart teaches in Figs. 1-5 (Figs. 1 and 5 shown above) and related text a method, comprising:
forming a cooling fluid channel (20, Figs. 1, 5 and col. 2, ll. 50-64) between a first sidewall and a second sidewall in a frame (12, Figs. 1, 5 and col. 2, ll. 50-64), the frame having at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the first sidewall alongside the cooling fluid channel (Fig. 5) and at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the second sidewall alongside the cooling fluid channel (20, Fig. 5);
disposing a first power electronics module (14, Figs. 1, 5 and col. 2, ll. 50-64) to cover the at least one opening in the first sidewall (Figs. 1 and 5) with a surface of a substrate (32, Figs. 1-2, 5 and col. 3, ll. 11-23) in the first power electronics module (14, Figs. 1-2 and 5) being exposed to the cooling fluid channel (20, Fig. 5) in the frame through the at least one opening in the first sidewall (Figs. 1 and 5);
coupling a first baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) to the substrate (32, Fig. 2) of the first power electronics module and including a first pin fin (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67);
disposing a second power electronics module (14, Figs. 1, 5 and col. 2, ll. 50-64) to cover the at least one opening in the second sidewall with a surface of a substrate in the second power electronics module being exposed to the cooling fluid channel (20, Fig. 5) in the frame through the at least one opening in the second sidewall (Figs. 1 and 5); and
coupling a second baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) to the substrate (32, Fig. 2) of the second power electronics module and including a second pin fin (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67).
Rinehart, however, does not explicitly teach that the second pin fin is in contact with the first pin fin.
Ushijima, in a similar field of endeavor, teaches in Fig. 14 and related text, a first baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a first semiconductor module (122, Fig. 14 and ¶[0057]) that includes a first pin fin (30, Fig. 14 and ¶[0031]) and second baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a second semiconductor module (124, Fig. 14 and ¶[0057]) that includes a second pin fin (30, Fig. 14 and ¶[0031]), wherein the second pin fin is in contact with the first fin pin in order to inhibit variation in the flow velocity distribution in the cooling medium passage (¶[0063]).
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art to include the second pin fin that is in contact with the first pin fin, as disclosed by Ushijima, in the package disclosed by Rinehart, in order to inhibit variation in the flow velocity distribution in the cooling medium passage.
Regarding claim 16 (15), the combined teaching of Rinehart and Ushijima discloses wherein forming the cooling fluid channel includes disposing an inlet port (Rinehart, 18, Fig. 1 and col. 2, ll. 50-64) at a first end of the frame and an outlet port (Rinehart, 22, Fig. 1 and col. 2, ll. 50-64) at a second end of the frame opposite the first end (Rinehart, Fig. 1).
Regarding claim 17 (16), the combined teaching of Rinehart and Ushijima discloses wherein disposing the first power electronics module (Rinehart, 14, Figs. 1 and 5) to cover the at least one opening in the first sidewall includes sealing of the at least one opening in the first sidewall by the surface of the substrate in the first power electronics module (Rinehart, Figs. 1 and 5).
Regarding claim 20 (15), the combined teaching of Rinehart and Ushijima discloses wherein disposing the first power electronics module to cover the at least one opening in the first sidewall further includes exposing the first pin fin on the first baseplate to the cooling fluid channel (Rinehart, 20, Figs. 1 and 5) in the frame (Rinehart, 12, Figs. 1 and 5).
Regarding claim 22 (15), the combined teaching of Rinehart and Ushijima further discloses aligning the first power electronics module (Rinehart, 14, Figs. 1 and 5 and Ushijima, Fig. 14) and the second power electronics module (Rinehart, Fig. 5 and Ushijima, Fig. 14) so that a top end surface of the first pin fin touches a top end surface of the second pin fin (Rinehart, Figs. 1 and 5 and Ushijima, Fig. 14).
Regarding claim 24, Rinehart teaches in Figs. 1-5 (Figs. 1 and 5 shown above) and related text a package comprising:
a frame (12, Figs. 1, 5 and col. 2, ll. 50-64) having a cooling fluid channel (20, Figs. 1, 5 and col. 2, ll. 50-64) therethrough, the cooling fluid channel being formed between a first sidewall and a second sidewall opposite the first sidewall (20, Figs. 1, 5 and col. 4, ll. 3-18), the frame having at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the first sidewall alongside the cooling fluid channel (20, Figs. 1 and 5) and at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the second sidewall alongside the cooling fluid channel (20, Figs. 1 and 5);
a first power electronics module (14, Figs. 1-2, 5 and col. 3, ll. 50-64) covering the at least one opening in the first sidewall (Figs. 1 and 5) with a surface of a substrate (32, Figs. 1-2, 5 and col. 3, ll. 11-23) in the first power electronics module being exposed to the cooling fluid channel (20, Figs. 1 and 5) in the frame through the at least one opening in the first sidewall (col. 4, ll. 3-18);
a first baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) coupled to the substrate (32, Fig. 2) of the first power electronics module and including an array of first pin fins (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67);
a second power electronics module (14, Figs. 1-2, 5 and col. 3, ll. 50-64) covering the at least one opening in the second sidewall (Figs. 1 and 5) with a surface of a substrate (32, Figs. 1-2, 5 and col. 3, ll. 11-23) in the second power electronics module being exposed to the cooling fluid channel (20, Figs. 1 and 5) in the frame through the at least one opening in the second sidewall (Figs. 1 and 5); and
a second baseplate (40 (44), Fig. 2 or 54, Fig. 4B and col. 3, ll. 36-67) coupled to the substrate (32, Fig. 2) of the second power electronics module and including an array of second pin fins (46, Fig. 2 or 52, Figs. 4A-4B and col. 3, ll. 36-67).
Rinehart, however, does not explicitly teach that the array of second pin fins is in contact with the array of first pin fins.
Ushijima, in a similar field of endeavor, teaches in Fig. 14 and related text, a first baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a first semiconductor module (122, Fig. 14 and ¶[0057]) that includes an array of first pin fins (30, Fig. 14 and ¶[0031]) and second baseplate (24, Fig. 14 and ¶[0031]) coupled to a substrate of a second semiconductor module (124, Fig. 14 and ¶[0057]) that includes an array of second pin fins (30, Fig. 14 and ¶[0031]), wherein the array of second pin fins is in contact with the array of first pin fins in order to inhibit variation in the flow velocity distribution in the cooling medium passage (¶[0063]).
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art to include the array of second pin fins that is in contact with the array of first pin fins, as disclosed by Ushijima, in the package disclosed by Rinehart, in order to inhibit variation in the flow velocity distribution in the cooling medium passage.
Response to Arguments
Applicant's arguments filed on May 12, 2026 have been fully considered but they are either moot in view of new grounds of rejection or not persuasive.
On page 10 of the filed response the Applicant argues that the “combination of Rinehart and Ushijima does not teach or suggest these structure limitations. Ushijima does not fill the gaps in Rinehart, and the combination fails to teach or suggest all the limitations of amended claims 9 and 22”. The examiner respectfully disagrees.
As discussed above, in the rejections of claims 1, 11 and 22, as well as rejections of claim 9 and 22, while Rinehart does not explicitly teach that a top end surface of the first pin fin touches a top end surface of the second pin fin, as required by claims 9 and 22, or more generally, that the second pin fin is in contact with the first fin pin, as required by claims 1, 11 and 24, Ushijima explicitly teaches that pin fins such as those disclosed by Rinehart can be spaced apart from one another or in contact with one another in order to control variation in the flow velocity distribution in the cooling medium passage. Accordingly, contrary to the Applicant’s argument Rinehart in combination with Ushijima teach all of elements of the amended, not only of the amended claims 1, 11 and 24 but also claims 9 and 22.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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