Prosecution Insights
Last updated: April 19, 2026
Application No. 18/055,123

POWER ELECTRONICS PACKAGE WITH DUAL-SINGLE SIDE COOLING WATER JACKET

Non-Final OA §102§103
Filed
Nov 14, 2022
Examiner
CIESLEWICZ, ANETA B
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
66%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
151 granted / 228 resolved
-1.8% vs TC avg
Minimal -0% lift
Without
With
+-0.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
31 currently pending
Career history
259
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
46.9%
+6.9% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
24.5%
-15.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 228 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species IIIB in the reply filed on January 6, 2026 is acknowledged. Claims 5-6, 8, 10, 18-19, 21 and 23 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claim Objections Claim(s) 9 is/are objected to because of the following informalities: With respect to claim 9, in line 5 of the claim an additional “so that” should be deleted. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 7, 11-17, 20 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rinehart et al. (US 7,197,819, hereinafter “Rinehart”). Regarding claim 1, Rinehart teaches in Fig. 1-5 (Figs. 1 and 5 shown below) and related text a package comprising: a frame (12, Fig. 1 and col. 2, ll. 50-64) having a first sidewall and a second sidewall opposite the first sidewall, the frame having at least one opening (16, Fig. 1 and col. 2, ll. 50-64) in the first sidewall and at least one opening (16, Fig. 1 and col. 2, ll. 50-64) in the second sidewall ; a first power electronics module (14, Figs. 1, 5 and col. 2, ll. 50-64) covering the at least one opening in the first sidewall (Figs. 1 and 5) with a surface of a substrate (32, Fig. 2 and col. 3, ll. 11-20) in the first power electronics module being exposed to an interior of the frame through the at least one opening (16, Figs. 1 and 5) in the first sidewall (Figs. 1 and 5); and a second power electronics module (14, Figs. 1, 5 and col. 2, ll. 50-64) covering the at least one opening in the second sidewall (Figs. 1 and 5) with a surface of a substrate (32, Fig. 2 and col. 3, ll. 11-20) in the second power electronics module being exposed to an interior of the frame through the at least one opening in the second sidewall (Figs. 1 and 5), the first sidewall, the surface of the substrate of the first power electronics module, the second sidewall, and the surface of the substrate of the second power electronics module collectively defining a cooling fluid channel (20, Figs. 1, 5 and col. 2, ll. 50-64) through the frame. PNG media_image1.png 450 594 media_image1.png Greyscale PNG media_image2.png 448 713 media_image2.png Greyscale Regarding claim 2 (1), Rinehart teaches wherein the surface of the substrate (32, Figs. 1-2 and col. 3, ll. 11-20) in the first power electronics module is a first surface of the substrate, and the first power electronics module is a single side direct cooled (SSDC) package including a power semiconductor device (30, Fig. 2 and col. 3, ll. 11-20) mounted on a second surface of the substrate opposite the first surface of the substrate (Figs. 1-2 and 5). Regarding claim 3 (1), Rinehart further teaches: an inlet port (18, Fig. 1 and col. 2, ll. 50-64) disposed at a first end of the frame (12, Fig. 1); and an outlet port (22, Fig. 1 and col. 2, ll. 50-64) disposed at a second end of the frame (12, Fig. 1) opposite the first end. Regarding claim 4 (1), Rinehart teaches wherein the surface of the substrate in the first power electronics module covering the at least one opening seals the at least one opening in the first sidewall alongside the cooling fluid channel (Figs. 1, 5). Regarding claim 7 (1), Rinehart teaches wherein a baseplate (40, Figs. 1, 5, col. 3, ll. 36-67) is attached to the surface of the substrate (32, Fig. 2) of the first power electronics module exposed to the cooling fluid channel (20, Fig. 5) in the frame and the baseplate includes at least one pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extending from the baseplate into the cooling fluid channel (Figs. 1 and 5). Regarding claim 11, Rinehart teaches in Figs. 1-5 (Figs. 1 and 5 shown above) a package comprising: a frame (12, Figs. 1, 5 and col. 2, ll. 50-64) having a cooling fluid channel (20, Fig. 5 and col. 2, ll. 50-64) therethrough, the cooling fluid channel being formed between a first sidewall and a second sidewall opposite the first sidewall (Figs. 1 and 5), the frame including a first plurality of openings (16, Figs. 1, 5 and col. 2, ll. 50-64) disposed in a first row in the first sidewall alongside the cooling fluid channel and a second plurality (Figs. 1, 5, col. 2, ll. 50-64) of openings disposed in a second row in the second sidewall alongside the cooling fluid channel opposite the first sidewall (Figs. 1 and 5); a first plurality of power electronics modules (14, Figs. 1, 5 and col. 2, ll. 50-64) disposed alongside the first sidewall over the first plurality of openings in the first sidewall (col. 2, ll. 50-64) with each of the first plurality of openings exposing a surface of a substrate (32, Figs. 1, 2, 5 and col. 3, ll. 11-22) in a corresponding one of the first plurality of power electronics modules to the cooling fluid channel (20, Figs. 1 and 5) in the frame (12, Figs. 1 and 5); and a second plurality of power electronics modules (14, Figs. 1, 5 and col. 2, ll. 50-64) disposed alongside the second sidewall over the second plurality of openings in the second sidewall (col. 2, ll. 50-64) with each of the second plurality of openings exposing a surface of a substrate in a corresponding one of the second plurality of power electronics modules to the cooling fluid channel in the frame (20, Figs. 1 and 5). Regarding claim 12 (11), Rinehart teaches wherein a baseplate (40, Figs. 1, 5, col. 3, ll. 36-67) with pin fins (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) is attached to the surface of the substrate (32, Fig. 2, 54, Fig. 4B) in each of the first plurality of power electronics modules (14, Fig. 2 and 5) and the surface of the substrate (32, Figs. 1 and 5) in each of the second plurality of power electronics modules being exposed to the cooling fluid channel (20, Figs. 1 and 5) in the frame (12, Figs. 1 and 5). 40, Figs. 1, 5, col. 3, ll. 36-67) is attached to the surface of the substrate (32, Fig. 2) of the first power electronics module exposed to the cooling fluid channel (20, Fig. 5) in the frame and the baseplate includes at least one pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extending from the baseplate into the cooling fluid channel (Figs. 1 and 5). Regarding claim 13 (11), Rinehart teaches wherein each of the first plurality of power electronics modules and each of the second plurality of power electronics modules is a single side direct cooled (SSDC) package including a power semiconductor device (30, Fig. 2 and col. 3, ll. 11-23) mounted on a surface of the substrate (32, Fig. 2) opposite the surface of the substrate exposed to the cooling fluid channel in the frame (Figs. 1-2 and 5). Regarding claim 14 (11), Rinehart taches wherein the first plurality of power electronics modules and the second plurality of power electronics modules each include three single side direct cooled (SSDC) packages (Figs. 1 and 5). Regarding claim 15, Rinehart teaches in Figs. 1-5 (Figs. 1 and 5 shown above) and related text a method, comprising: forming a cooling fluid channel (20, Figs. 1, 5 and col. 2, ll. 50-64) between a first sidewall and a second sidewall in a frame (12, Figs. 1, 5 and col. 2, ll. 50-64), the frame having at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the first sidewall alongside the cooling fluid channel (Fig. 5) and at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the second sidewall alongside the cooling fluid channel (20, Fig. 5); disposing a first power electronics module (14, Figs. 1, 5 and col. 2, ll. 50-64) to cover the at least one opening in the first sidewall (Figs. 1 and 5) with a surface of a substrate (32, Figs. 1-2, 5 and col. 3, ll. 11-23) in the first power electronics module (14, Figs. 1-2 and 5) being exposed to the cooling fluid channel (20, Fig. 5) in the frame through the at least one opening in the first sidewall (Figs. 1 and 5); and disposing a second power electronics module (14, Figs. 1, 5 and col. 2, ll. 50-64) to cover the at least one opening in the second sidewall with a surface of a substrate in the second power electronics module being exposed to the cooling fluid channel (20, Fig. 5) in the frame through the at least one opening in the second sidewall (Figs. 1 and 5). Regarding claim 16 (15), Rinehart teaches wherein forming the cooling fluid channel includes disposing an inlet port (18, Fig. 1 and col. 2, ll. 50-64) at a first end of the frame and an outlet port (22, Fig. 1 and col. 2, ll. 50-64) at a second end of the frame opposite the first end (Fig. 1). Regarding claim 17 (16), Rinehart teaches wherein disposing the first power electronics module (14, Figs. 1 and 5) to cover the at least one opening in the first sidewall includes sealing of the at least one opening in the first sidewall by the surface of the substrate in the first power electronics module (Figs. 1 and 5). Regarding claim 20 (15), Rinehart teaches wherein disposing the first power electronics module to cover the at least one opening in the first sidewall includes attaching a baseplate (40, Fig. 2 and col. 3, ll. 36-54) to the surface of the substrate (32, Fig. 2) in the first power electronics module and exposing the baseplate to the cooling fluid channel (20, Figs. 1 and 5) in the frame (12, Figs. 1 and 5), and wherein the baseplate includes at least one pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extending from the baseplate into the cooling fluid channel (Figs. 1 and 5). Regarding claim 24, Rinehart teaches in Figs. 1-5 (Figs. 1 and 5 shown above) and related text a package comprising: a frame (12, Figs. 1, 5 and col. 2, ll. 50-64) having a cooling fluid channel (20, Figs. 1, 5 and col. 2, ll. 50-64) therethrough, the cooling fluid channel being formed between a first sidewall and a second sidewall opposite the first sidewall (20, Figs. 1, 5 and col. 4, ll. 3-18), the frame having at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the first sidewall alongside the cooling fluid channel (20, Figs. 1 and 5) and at least one opening (16, Figs. 1, 5 and col. 2, ll. 50-64) in the second sidewall alongside the cooling fluid channel (20, Figs. 1 and 5); a first power electronics module (14, Figs. 1-2, 5 and col. 3, ll. 50-64) covering the at least one opening in the first sidewall (Figs. 1 and 5) with a surface of a substrate (32, Figs. 1-2, 5 and col. 3, ll. 11-23) in the first power electronics module being exposed to the cooling fluid channel (20, Figs. 1 and 5) in the frame through the at least one opening in the first sidewall (col. 4, ll. 3-18); and a second power electronics module (14, Figs. 1-2, 5 and col. 3, ll. 50-64) covering the at least one opening in the second sidewall (Figs. 1 and 5) with a surface of a substrate (32, Figs. 1-2, 5 and col. 3, ll. 11-23) in the second electronics module being exposed to the cooling fluid channel (20, Figs. 1 and 5) in the frame through the at least one opening in the second sidewall (Figs. 1 and 5). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Reinhart as applied to claims 1 and 15 above, and further in view of Ushijima et al. (US 2016/0104654, hereinafter “Ushijima”). Regarding claim 9 (1), teaching of Rinehart was disclosed above in the rejection of claim 1 and further includes wherein the first power electronics module (14, Fig. 1 and col. 2, ll. 50-64) includes a first baseplate (40, Figs. 1, 5, col. 3, ll. 36-67) having at least a first pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extending therefrom into the cooling fluid channel (20, Figs. 1 and 5) and the second power electronics module (14, Fig. 1 and col. 2, ll. 50-64) includes a second baseplate (40, Figs. 1, 5, col. 3, ll. 36-67) having at least a second pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extending therefrom into the cooling fluid channel, and wherein the first baseplate and the second baseplate are aligned (Fig. 5). While Rinehart does not explicitly teach that that a top end surface of the first pin fin touches a top end surface of the second pin fin, when the first baseplate is aligned with the second baseplate, aligning the first baseplate and the second baseplate so that the a top end surface of the first pin fin touches a top end surface of the second pin fin would have been within the capabilities of one of ordinary skill in the art in order to inhibit variation in a flow velocity distribution in the cooling fluid channel, as evidenced by Ushijima (¶[0062]). Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to align the first baseplate and the second baseplate disclosed by Rinehart so that the a top end surface of the first pin fin touches a top end surface of the second pin fin, as disclosed by Ushijima, in order to inhibit variation in a flow velocity distribution in the cooling fluid channel. Regarding claim 22 (15), Rinehart teaches wherein the first power electronics module (14, Figs. 1 and 5) includes a first baseplate (40, Figs. 1-2, 5 and col. 3, ll. 36-54) having at least a first pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extending therefrom into the cooling fluid channel (20, Figs. 1 and 5) and the second power electronics module includes a second baseplate (40, Figs. 1-2, 5 and col. 3, ll. 36-54) having at least a second pin fin (46, Fig. 2, 52, Fig. 4B and col. 3, ll. 36-67) extending therefrom into the cooling fluid channel (20, Figs. 1 and 5), and wherein the method further includes aligning the first power electronics module and the second power electronics module (Fig. 5). While Rinehart does not explicitly teach that a top end surface of the first pin fin touches a top end surface of the second pin fin, when the first baseplate is aligned with the second baseplate, aligning the first baseplate and the second baseplate so that the a top end surface of the first pin fin touches a top end surface of the second pin fin would have been within the capabilities of one of ordinary skill in the art in order to inhibit variation in a flow velocity distribution in the cooling fluid channel as evidenced by Ushijima (¶[0062]). Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to align the first baseplate and the second baseplate disclosed by Rinehart so that the a top end surface of the first pin fin touches a top end surface of the second pin fin, as disclosed by Ushijima, in order to inhibit variation in a flow velocity distribution in the cooling fluid channel. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.B.C/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Nov 14, 2022
Application Filed
Feb 09, 2026
Non-Final Rejection — §102, §103
Apr 10, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
66%
With Interview (-0.4%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 228 resolved cases by this examiner. Grant probability derived from career allow rate.

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