DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Final Action
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed 11/24/2025 have been fully considered but they are not persuasive.
The applicant amended claims 1-3, 7-8 & 15 have been amended with newly added limitations thus mood.
Applicant argues:
Argument 1: Applicant submits that (Claim 14) “The Wong reference does not teach or suggest forming a variable gain amplifier including an input receiving an input signal and an open-conduction output over the substrate. In Wong, input stage 12 receives an input signal at terminals 14 and 16 and provides an output signal at terminals 76 and 78. However, input stage 12 in Wong is not a variable gain amplifier, as would be understood by a person skilled in the art. There is no disclosure in Wong that the gain of input stage 12 is variable or selectable. In addition, terminals 76 and 78 are not an open-conduction output. Terminals 76 and 78 are connected through resistor 58 and 60 to power supply conductor 74 and do not constitute an open-conduction output, as would be understood by a person skilled in the art”.
Examiner respectfully disagrees all of the allegations as argued. Examiner, in his previous office action, gave detail explanation of claimed limitation and pointed out exact locations in the cited prior art.
Examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification.
Interpretation of Claims-Broadest Reasonable Interpretation During patent examination, the pending claims must be ‘given the broadest reasonable interpretation consistent with the specification.’ Applicant always has the opportunity to amend the claims during prosecution and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified.
In response to applicant's argument, examiner respectfully submits that:
With respect to the argument 1, it is clearly that Fig. 1 of Wong does discloses a variable gain amplifier including an input receiving an input signal (see terminal 16, 14 of Fig. 1, Wong) and an open-conduction output (output terminal 78 and 76, it is noted that the applicant has not clearly define an open-conduction output, thus open-conduction output may be read on any output terminal) over the substrate integrated circuit (see, integrated circuit, see column 2, lines 46-48).
Wong does disclosure the gain of input stage 12 is variable or selectable, it is noted that the gain of the input stage 12 which having current source 51, 62, 55, 66 which controls by vbias signal at terminal 70, thus currents being adjusted by the vbias thus current will be adjusted to the differential 40 and the gain of the differential 40 would be affected by adjusting current source 66, at least for the reasons above, the input stage 12 may be operating as variable gain amplifier.
It is noted that terminals 76 and 78 may be read as an open-conduction output since the limitation of “an open-conduction output” as cited in claim 1 which merely stated but does not specified an open-conduction output is. Terminals 76 and 78 are connected through resistor 58 and 60 to power supply conductor 74 and do constitute an open-conduction output since claim 14 does not exclude the resistors 58 and 60 and hence the rejected claim 14 is still appear valid and make it final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 & 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kennan et al. (US 20210250004 A1).
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Regarding claims 1 & 7, Kennan et al. discloses in Figs. 3C & 4 an amplifier circuit or a semiconductor device, comprising:
a variable gain amplifier (Fig. 4, amplifier section 304 which operates as variable gain amplifier) including an input (terminals 308A, 308B) receiving an input signal and an open-conduction output (terminals 312A and 312B) having no connection within the variable gain amplifier (amplifier section 304 operating as variable gain amplifier) to a first power supply terminal (terminal 320); and
an output stage (Fig. C, a circuit includes elements 130, 120A-P to 120N-P, 120A-N to 120N-N) including an input (terminal between element 120A-P and 120B-P; and a terminal between elements 120A-N and 120B-N) coupled to the open- conduction output of the variable gain amplifier and an output (terminal Out of Fig. 3C) providing an output signal of the amplifier circuit.
Claims 14 & 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wong (US 5,550,513 A, of record).
Regarding claim 14, Wong (Figs. 1, 3 & 5) discloses a method of making a semiconductor device (integrated circuit, see column 2, lines 46-48) comprising an amplifier circuit (Figs. 1, 3 & 5), including: providing a substrate (see column 2, lines 43-44, fabricated in AlGaAs/GaAs utilizing an HBT process); forming a variable gain amplifier (Fig. 1) including an input receiving (terminals 14, & 16) an input signal and an open-conduction output (nodes 78, 76, it is noted that “an open-conduction output” which is not clear specific defined this which considered a merely an output node, also noted that the applicant more clarified in claim 1). over the substrate (see column 2, lines 43-44, fabricated in AlGaAs/GaAs utilizing an HBT process); and forming an output stage (five-stage differential distributed amplifier of Fig. 3) including an input (input terminal INPUT- and input terminal INPU+) coupled to the open-conduction output of the variable gain amplifier and an output (OUTPUT + and OUPUT- of Fig. 3) providing an output signal of the amplifier circuit over the substrate.
Regarding claim 17, Wong (Figs. 1, 3 & 5) discloses wherein forming the output stage includes: providing a first input transmission line (TL1) including an input coupled to the first terminal of the open-conduction output of the variable gain amplifier; providing a second input transmission line (TL2) including an input coupled to an output of the first input transmission line (TL1) at a first node (N1); providing a first gain cell (Cel1) including an input coupled to the first node (N1); and providing a first output transmission line (TL01) including an input coupled to an output of the first gain cell (Cel1) and an output providing a first component of the output signal (see terminal 80)of the amplifier circuit.
Regarding claim 18, Wong (Figs. 1, 3 & 5) discloses wherein forming the output stage further includes: providing a third input transmission line (TL3) including an input coupled to the second terminal of the open-conduction output of the variable gain amplifier; providing a fourth input transmission line (TL4) including an input coupled to an output of the third input transmission line at a second node (N2); providing a second gain cell (Cel2) including an input coupled to the second node; providing a termination circuit (see Fig. 5, the termination circuit includes resistors 232 and 234) coupled to an output of the second input transmission line (TL2) and to an output of the fourth input transmission line (TL4); and providing a second output transmission line (TL02) including an input coupled to an output of the second gain cell (Cel2) and an output providing a second component of the output signal of the amplifier circuit.
Regarding claim 19, Wong (Figs. 1, 3 & 5) discloses wherein the termination circuit includes: providing a first resistor (232) coupled between the output of the second input transmission line and a voltage source(return potential ground); and providing a second resistor coupled between the output of the fourth input transmission line and the voltage source (return potential ground).
Regarding claim 20, Wong (Figs. 1, 3 & 5) discloses wherein the first input transmission line (TL1 which includes inductor, see Fig. 3) includes inductive properties.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wong in view of Everton (US 8,742,846 B1, of record) and further in view of Moonen et al. (US 8,154,343 B2, of record) (hereinafter called Moonen).
Regarding claim 16, the combination (Wong in view of Everton) furth discloses wherein the variable gain amplifier further includes: a first resistor (48, Fig. 1 of Everton) coupled between a second conduction terminal of the first transistor (Q0, Fig. 1 of Everton) and a power supply terminal (Vp); a second resistor (resistor 50) coupled between a second conduction terminal of the second transistor (Q1, Fig. 1 of Everton) and the power supply terminal except for a capacitor coupled between the second conduction terminal of the first transistor and the second conduction terminal of the second transistor.
Moonen (Fig. 3) discloses an amplifier circuit comprising transistors Q0 and Q1 wherein a capacitor 201 being connected between emitter terminals of transistors Q0 and Q1.
The combination (Wong in view of Everton and Moonen are analogous art because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of the combination (Wong in view of Everton) to have included a capacitor coupled between the second conduction terminal of the first transistor (Q0) and the second conduction terminal of the second transistor (Q1) as taught by Moonen. Such a modification would have imparted the advantageous benefit of reducing noises, power consumption and improving the circuit performance, see abstract, as taught by Moonen, to the combination (Wong in view of Everton) reference, thereby suggesting the obviousness of such a modification.
Allowable Subject Matter
Claims 2-6, 8-13 & 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA J LINDGREN BALTZELL can be reached at (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843