DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over TSAI et al. (US PUB. 2020/0343198) in view of LIU et al. (US Pub. 2015/0380357).
Regarding claim 1, TSAI teaches a memory device package, comprising:
a substrate 102 having a first chip region (11 or 12), a second chip region (12 or 11), and a first scribe line region 13 connected between the first chip region and the second chip region (Fig. 1K);
a first memory chip 130 disposed over the first chip region 11 (Fig. 1G & Fig. 1K);
a second memory chip 230 disposed over the second chip region 12 (Fig. 1G & Fig. 1K).
TSAI is silent on guard rings embedded in the substrate and disposed across a boundary between the first chip region and the first scribe line region. However, LIU teaches in Fig. 8B-8C, guard rings 101a embedded in a substrate 101 and disposed across a boundary between a first chip region and a first scribe line region 902. This has the advantage of providing protection and preventing cracks to propagate towards the chip/die region. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of TSAI with the guard rings as taught by LIU, so as to provide protection for the semiconductor device.
Regarding claim 2, the combination of TSAI and LIU teaches the memory device package of claim 1, wherein the first memory chip 130 comprises a first capacity and the second memory chip 230 comprises a second capacity, and the first chip and the second chip are bundled together to form the memory device package having a third capacity (Fig. 1K).
Regarding claim 3, the combination of TSAI and LIU teaches the memory device package of claim 2, wherein the third capacity equals to a sum of the first capacity and the second capacity (Fig. 1K).
Claims 4-7 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over TSAI and LIU as applied to claim 1 above, and in further view of Schulz et al. (US PUB. 2018/0181524).
Regarding claim 4, the combination of TSAI and LIU does not teach the memory device package of claim 1, further comprising: a conductive wire disposed outside of the substrate, wherein the first memory chip 130 and the second memory chip 230 are electrically connected through the conductive wire; wherein the conductive wire extends across the first scribe line region. However, Schulz teaches in Fig. 4, a conductive wire 84 disposed outside of a substrate 16 (Fig. 2 & Fig. 4), wherein a first memory chip 12 and a second memory chip 14 are electrically connected through the conductive wire 84; wherein the conductive wire 84 extends across the first scribe line region (the space between the first and second memory chips 12 & 14 can be read as a scribe line region, see Fig. 2-4). This has the advantage of transferring data signals between a first and second integrated circuit (IC) dies 12 & 14. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of TSAI and LIU with the conductive wire as taught by Schulz, so as to enable transfer of data signals between a first IC die and a second IC die.
Regarding claim 5, the combination of TSAI, LIU and Schulz teaches the memory device package of claim 4, wherein the conductive wire 84 is configured to combine a capacity of the first memory chip and a capacity of the second memory chip (TSAI’s Fig. 1K and Schulz’s Fig. 2-4).
Regarding claim 6, the combination of TSAI and LIU does not teach the memory device package of claim 1, further comprising: a circuit layer disposed in the substrate, wherein the first memory chip and the second memory chip are electrically connected through the circuit layer; wherein the circuit layer extends across the first scribe line region. However, Schulz teaches in Fig. 1-3, a circuit layer 34 disposed in a substrate 16, wherein a first memory chip 12 and a second memory chip 14 are electrically connected through the circuit layer 34 (dies 12 & 14 can be either memory or logic dies); wherein the circuit layer extends across the first scribe line region (the space between the first and second memory chips can be a scribe line region). This has the advantage of enabling communicating between a fist and second integrated circuit (IC) die. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of TSAI and LIU with the circuit layer as taught by Schulz, so as to enable communication between a first IC die and a second IC die.
Regarding claim 7, the combination of TSAI, LIU and Schulz teaches the memory device package of claim 6, wherein a conductive wire 34 is configured to combine a capacity of the first memory chip and a capacity of the second memory chip (TSAI’s Fig. 1K and Schulz’s Fig, 1-3).
Regarding claim 12, TSAI teaches a memory device package 100a, comprising:
a substrate 102 having a first scribe line region 13 (Fig. 1K);
a first memory chip 130 disposed over the substrate 102 (Fig. 1G & Fig. 1K);
a second memory chip 230 disposed over the substrate 102 (Fig. 1K).
TSAI does not teach (i) wherein the second memory chip 230 is electrically connected with first memory chip 130 through a circuit layer extending across the first scribe line region; and (ii) guard rings embedded in the substrate and disposed across a boundary between the first memory chip and the first scribe line region.
Schulz teaches (i), wherein a second memory chip 14 (see Fig. 1-3) is electrically connected with first memory chip 12 (dies 12 & 14 can be either memory or logic dies) through a circuit layer 34 extending across the first scribe line region (the space between the first and second memory chips can be a scribe line region). This has the advantage of enabling communicating between a fist and second integrated circuit (IC) die. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of TSAI with the circuit layer as taught by Schulz, so as to enable communication between a first IC die and a second IC die.
LIU teaches (ii) guard rings 101a, in Fig. 8B-8C, embedded in a substrate 101 and disposed across a boundary between a first chip and a first scribe line region 902. This has the advantage of providing protection and preventing cracks to propagate towards the chip/die region. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of TSAI with the guard rings as taught by LIU, so as to provide protection for the semiconductor device.
Regarding claim 13, the combination of TSAI, Schulz and LIU teaches the memory device package of claim 12, wherein the first scribe line region is disposed between the first memory chip 130/12 and the second memory chip 230/14, and a conductive layer (one of the conductive layers of 34) is configured to combine a capacity of the first memory chip and a capacity of the second memory chip to form a bundled memory chip (TSAI’s Fig. 1K and Schulz’s Fig. 1-3).
Response to Arguments
Applicant’s arguments with respect to claims 1-7 & 12-13 have been considered but are moot in light of new grounds of rejection.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818