DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 8-10 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 defines in the preamble “..defects of a semiconductor” but in the body of the claim
defines “defects of a semiconductor” has antecedent issues which should be “the defects of the semiconductor”. Appropriate correction is required.
Claim 1 defines “a second chamber being constructed from the main body, the second flange and the chamber housing” and in the last line defines “the second chamber is positioned between the first flange and the second flange” is indefinite as shown in Fig. 1 only a portion of the second chamber (the main body portion) is positioned between the first flange and the second flange. Appropriate correction is required.
Claim 8 defines predetermined pressure and a predetermined temperature but no specific reaction gas, pressure, temperature range to be considered as predetermined. Therefore any reaction gas, any temperature and pressure will be considered as the claimed limitations.
Claims 8-10 are also rejected being dependent on rejected claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-9 are rejected under 35 U.S.C. 103 as being obvious over Yamaga et al (US Patent 5,484,484) in view of Yuasa et al (WO 2017/056243A1).
Regarding claim 1: Yamaga teaches in Fig. 1about an apparatus for repairing defects of a semiconductor, comprising:
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a chamber housing 23, having an opening (As marked through which the boat 34 moves up and down) and a plurality of heating devices 22;
a gate component disposed at the opening, the gate component including:
a main body 3;
a first flange (as marked) connected to a top portion of the main body, an outer surface of the first flange being overlapped with an inner surface of the chamber housing (as shown), a first chamber being constructed from the main body, the first flange and the chamber housing (as marked), and the first chamber being configured to accommodate at least a semiconductor element W;
at least a first sealing element 32a disposed at a top surface of the first flange;
a second flange (as marked), which is connected to a side portion of the main body3 and is lower than the first flange (As shown), an outer surface of the second flange being overlapped with the inner surface of the chamber housing,
a second chamber being constructed from the main body, the second flange and the chamber housing (as marked), and the heating devices being not overlapped with the second chamber in a direction parallel to a protruding direction of the second flange (As shown); and
at least a second sealing element 32 disposed at a top surface of the second flange;
a first gas-intake pipe 4/6 connected to the first chamber, the first gas-intake pipe being configured to introduce a reaction gas to the first chamber; and
a first exhaust pipe 5/7 connected to the first chamber, the first exhaust pipe being configured to release a gas composition and/or the reaction gas in the first chamber,
wherein defects of a semiconductor are repaired by using the reaction gas in the first
chamber, and
wherein the first flange and the second flange are spaced apart from each other (As shown), and
the second chamber is positioned between the first flange and the second flange (as part of main body 3 is part of 2nd chamber which is between 32a and 32).
Yamaga does not explicitly talk about repairing defects of a semiconductor.
Yuasa teaches in treatment process S410 of annealing in the treatment chamber to repairs the crystal defect portion.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to realize from Yuasa’s teachings that annealing in Yamaga’s apparatus would inherently repair any defects in the polycrystalline structure of the semiconductor wafer.
Regarding claim 8: Yamaga teaches in abstract about wherein a pressure and a temperature of the first chamber are a predetermined pressure (a predetermined reduced-pressure status) and a predetermined temperature (a high temperature of, for example, 780.degree. C.) of the reaction gas, respectively.
Regarding claim 9: Yamaga teaches in Fig. 1, wherein the at least a semiconductor element includes a wafer W, and Yuasa teaches the wafer includes a semiconductor layer or an insulating layer and/or the wafer has been treated with an ion implantation.
Claim 10 is rejected under 35 U.S.C. 103 as being obvious over Yamaga et al (US Patent 5,484,484) in view of Yuasa et al (WO 2017/056243A1) and further in view of Kim et al (US 2013/0302916A1)
Regarding claim 10: Yamaga teaches about the defects are impurities such as particles (col.2, lines 45-50).
Yamaga does not explicitly talk about wherein the defects includes at least one of interface trap, dislocation, and dangling bond, and the at least a semiconductor element includes at least one of the defects.
Kim teaches in [0008] wherein the defects includes at least one of interface trap, dislocation, and dangling bond, and the at least a semiconductor element includes at least one of the defects.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to realize from Kim’s teachings that annealing in Yamaga’s apparatus to improve the device performance. For example, it could increase the device's lifetime and its transconductance, and it can decrease the number of dangling bonds (Kim, [0022]).
Response to Arguments
Applicant’s arguments, see page 9 filed on 10/29/2025, with respect to the rejection(s) of claim(s) 1, 8 under 112, 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yamaga et al (US Patent 5,484,484) and under new 112 (b) issues.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897