DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 19 March 2025 has been entered.
Amendment
Acknowledgment is made of applicant’s Amendment, filed 25 February 2025. The changes and remarks disclosed therein have been considered.
No claims have been cancelled or added by the Amendment. Therefore, claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 10-14, 18-20 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Reohr et al (US 6,269,040 B1 hereinafter “Reohr”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Reohr, for example in Figs. 1-8, discloses a structure (see for in Figs. 3, 4A related in Figs. 1-2, 5-8) comprising: columns of memory cells (e.g., cell columns 322, 324, 342, 344; in Figs. 1A, 4A); bitlines for the columns (e.g., the lines are connected to switch circuit 31/41/43; in Figs. 3, 4A related in Figs. 1-2, 5-8), respectively, wherein each bitline is connected to all memory cells in a corresponding column (within memory array 30/40; in Figs. 3, 4A related in Figs. 1-2, 5-8); a sense amplifier (e.g., SA 39/46/48; in Figs. 3, 4A related in Figs. 1-2, 5-8); and a switch circuit electrically connected to the bitlines (e.g., switch circuit 41, 43, 45, 47; in Fig. 4A related in Figs. 1-3, 5-8) for a group of the columns (e.g., cell columns CLa, CL1, CL0, CLc; in Fig. 4A related in Figs. 1-3, 5-8) and to the sense amplifier (see for example in Fig. 4A related in Figs. 1-3, 5-8), wherein the group includes column pairs (e.g., cell column pair CLa, CL1 and cell column pair CL0, CLc; in Fig. 4A related in Figs. 1-3, 5-8), wherein each column pair includes two adjacent columns (e.g., cell columns CL1, CL0; in Fig. 4A related in Figs. 1-3, 5-8), wherein the two adjacent columns of different column pairs in the group are different such that each column in the group is only within one column pair in the group (e.g., cell column pair CLa, CL1 and cell column pair CL0, CLc; in Fig. 4A related in Figs. 1-3, 5-8), and wherein the switch circuit establishes electrical connections between the sense amplifier and any of a single bitline for any single column of the group to enable single cell sensing by the sense amplifier and two bitlines for any column pair the group to enable twin cell sensing by the sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8).
The structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
PNG
media_image1.png
479
652
media_image1.png
Greyscale
Regarding claim 2, Reohr, for example in Figs. 1-8, discloses wherein the single cell sensing includes sensing, by the sense amplifier, of a data value stored in a single memory cell in the single column of the group (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), and wherein the twin cell sensing includes sensing, by the sense amplifier, of a data value stored in two memory cells in the two adjacent columns, respectively, of a column pair (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above). Also, the structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, Reohr, for example in Figs. 1-8, discloses wherein the group of the columns comprises an even number of the columns (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above). Also, the structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 11, Reohr, for example in Figs. 1-8, discloses a structure (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8) comprising: memory cells arranged in columns and rows (within memory array 30/40; in Figs. 3, 4A related in Figs. 1-2, 5-8); bitlines for the columns, respectively, wherein each bitline is connected to all memory cells in a corresponding column (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); sense amplifiers for groups of the columns (e.g., SA; in Figs. 3, 4A related in Figs. 1-2, 5-8), respectively, wherein each group of the columns includes column pairs (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), wherein each column pair includes two adjacent columns (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), and wherein the two adjacent columns of different column pairs in the group are different such that each column in the group is only within one column pair in the group (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); and switch circuits for the groups of the columns, respectively (switch circuit 41, 43, 45, 47; in Fig. 4A related in Figs. 1-3, 5-8), wherein each switch circuit is electrically connected to the bitlines for a corresponding group of the columns and to a corresponding sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), and establishes electrical connections between the corresponding sense amplifier and any of a single bitline for any single column of the corresponding group to enable single cell sensing by the corresponding sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above) and two bitlines for any column pair of the corresponding group to enable twin cell sensing by the corresponding sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above).
The structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, Reohr, for example in Figs. 1-8, discloses wherein the single cell sensing includes sensing, by the corresponding sense amplifier, of a data value stored in a single memory cell in the single column of the corresponding group by comparing a data signal from the single bitline for the single column to a reference signal (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), and wherein the twin cell sensing includes sensing, by the corresponding sense amplifier, of a data value stored in two memory cells in two columns, respectively, of a column pair in the corresponding group by comparing a true data signal from a first bitline for a first column of the column pair to a complement data signal from a second bitline for a second column of the column pair (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above). Also, the structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, Reohr, for example in Figs. 1-8, discloses wherein at least one row of the memory cells includes a set of twin cells with each twin cell in the set being in a different group of the groups of the columns and storing a single bit of a multi-bit trim signal (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), and wherein, in response to specific primary and secondary enable signals received by the switch circuits upon power up, the switch circuits enable concurrent twin cell sensing by the sense amplifiers of all the twin cells in the set to output the multi-bit trim signal (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above). Also, the structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, Reohr, for example in Figs. 1-8, discloses further comprising a register, wherein the register receives the multi-bit trim signal from the sense amplifiers and stores the multi-bit trim signal (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above). Also, the structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 18, Reohr, for example in Figs. 1-8, discloses further comprising source lines for the columns, wherein the memory cells in any column are connected between a source line and the bitline for the column, and wherein the memory cells comprise any of: an access transistor and a programmable resistor connected in series; and a threshold voltage-programmable transistor (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above). Also, the structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 19, Reohr, for example in Figs. 1-8, discloses wherein each group of the columns comprises an even number of the columns (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above). Also, the structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 20, Reohr, for example in Figs. 1-8, discloses a structure (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8) comprising: memory cells arranged in columns and rows (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); bitlines for the columns, respectively (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), wherein each bitline is connected to all memory cells in a corresponding column (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); sense amplifiers for groups of the columns, respectively, wherein each group of the columns includes column pairs (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), wherein each column pair includes two adjacent columns, and wherein the two adjacent columns of different column pairs in the group are different such that each column in the group is only within one column pair in the group (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); switch circuits for the groups of the columns, respectively, wherein each switch circuit is electrically connected to the bitlines for a corresponding group of the columns and to a corresponding sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); and a column decoder in communication with the switch circuits, wherein the column decoder outputs primary and secondary read mode enable signals to the switch circuits (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), wherein, depending upon the primary and secondary read mode enable signals, at least one of the switch circuits establishes electrical connections between the corresponding sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above) and any of a single bitline for any single column of the corresponding group to enable single cell sensing by the corresponding sense amplifier and two bitlines for any column pair of the corresponding group to enable twin cell sensing by the corresponding sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above).
The structure in of the prior art (Reohr) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6, 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Reohr et al (US 6,269,040 B1 hereinafter “Reohr”) in view of Jung et al (US 8,203,869 B2 hereinafter “Jung”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 3, Reohr, for example in Figs. 1-8, discloses wherein the sense amplifier includes: a first input; and a second input (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above), and wherein the switch circuit includes: multiple input nodes electrically connected to the bitlines, respectively, for the group (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); a first output node electrically connected to a first input of the sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above); and a second output node electrically connected to a second input of the sense amplifier (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8, as discussed above).
However, Reohr is silent with regard to an additional input electrically connected to a reference generator.
In the same field of endeavor, Jung, for example in Figs. 1-6, discloses an additional input electrically connected to a reference generator (e.g., precharged to 3.3V; in Fig. 4 related in Figs. 1-3, 5-6).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Reohr such as interconnection network for connecting memory cells to sense amplifiers (see for example in Figs. 1-8 of Reohr) by incorporating the teaching of Jung such as bit line charge accumulation sensing for resistive changing memory (see for example in Figs. 1-6 of Jung), for the purpose of controlling the bit line charge accumulation sensing for magneto-resistive changing memory (Jung, see abstract). Also, the structure in of the prior art (Reohr and Jung) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, the above Reohr/Jung, combination discloses wherein, for the single cell sensing, the switch circuit establishes a first electrical connection between the first input of the sense amplifier and the single bitline of the single column within the group (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above) and further establishes a second electrical connection between the second input and the reference generator to enable a comparison, by the sense amplifier, of a data signal from a single memory cell in the single column to a reference signal from the reference generator (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above). Also, the structure in of the prior art (Reohr and Jung) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Reohr/Jung, combination discloses wherein, for the twin cell sensing, the switch circuit establishes a first electrical connection between the first input and a first bitline of a first column of the column pair, disconnects the second input from the reference generator (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above), and establishes a second electrical connection between the second input and a second bitline of a second column of the column pair to enable a comparison (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above), by the sense amplifier, of a true data signal from a first memory cell in the first column and a complement data signal from a second memory cell in the second column (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above). Also, the structure in of the prior art (Reohr and Jung) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Reohr/Jung, combination discloses further comprising source lines for the columns, wherein the memory cells in any column are connected between a source line and the bitline for the column, and wherein the memory cells comprise any of: an access transistor and a programmable resistor connected in series; and a threshold voltage-programmable transistor (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above). Also, the structure in of the prior art (Reohr and Jung) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 15, the above Reohr/Jung, combination discloses further comprising an additional component having an adjustable output, wherein the additional component adjusts the adjustable output based on the multi-bit trim signal, and wherein the adjustable output is employed by the structure during subsequent operations (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above). Also, the structure in of the prior art (Reohr and Jung) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 16, the above Reohr/Jung, combination discloses wherein the additional component comprises a bias voltage generator connected to the sense amplifiers, and wherein the bias voltage generator outputs an adjustable bias voltage to the sense amplifiers (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above). Also, the structure in of the prior art (Reohr and Jung) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 17, the above Reohr/Jung, combination discloses wherein, prior to storage of the multi-bit trim signal in the register, the bias voltage generator outputs a nominal gate bias voltage, and wherein, following storage of the multi-bit trim signal in the register (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above), the bias voltage generator receives the multi-bit trim signal from the register and based on the multi-bit trim signal, outputs an adjusted gate bias voltage to the sense amplifiers to tune sense amplifier sensitivity (see for example in Figs. 3, 4A related in Figs. 1-2, 5-8 of Reohr and also see in Fig. 4 related in Figs. 1-3, 5-6 of Jung, as discussed above). Also, the structure in of the prior art (Reohr and Jung) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior arts of record fail to teach or suggest a structure as recited in claim 7, and particularly, wherein the switch circuit includes: a first sense line, wherein the first output node is electrically connected to the first sense line; a second sense line, wherein the second output node is electrically connected to the second sense line; for each column pair in the group, a first switch between a first bitline for a first column of the column pair and the first sense line; a second switch between the first bitline and the first sense line; a third switch between a first source line for the first column and ground; a fourth switch between the first source line of the first column and ground; a fifth switch between a second bitline for a second column of the column pair and the first sense line; a sixth switch between the second bitline and the second sense line; a seventh switch between a second source line for the second column and ground; and an eighth switch between the second source line and ground; and an additional switch between the reference generator and the second output node.
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection is made in view of Reohr and Jung.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THA-O H BUI whose telephone number is (571)270-7357. The examiner can normally be reached M-F 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER SOFOCLEOUS can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THA-O H BUI/Primary Examiner, Art Unit 2825 05/27/2026
Prosecution Insights