DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the RCE filed 2/10/2026 in which claims 1, 15, and 21 were amended.
Claims 1-9 and 12-24 remain pending with claims 15-24 remaining withdrawn and claims 1-9 and 12-14 presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-7, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Miyahara et al (US 2013/0001592 and Miyahara hereinafter) in view of Kobayashi et al (US 2019/0109227 and Kobayashi hereinafter).
As to claims 1-3, 5-7, and 12-14: Miyahara discloses [claim 1] a semiconductor device (Fig. 4), comprising: a substrate (2; [0026]) having a first conductivity type (n-type; [0026]); an epitaxial layer (comprising 3, 4, 5, and 6; [0026]-[0028]) on the substrate (2), wherein the epitaxial layer (comprising 3, 4, 5, and 6) has the first conductivity type (“has” is interpreted to mean comprising and portion 3 comprises the first conductivity type (n-type); [0026]-[0028]); a well region (4; [0028]) over the substrate (2), wherein the well region (4) extends downward from a top surface of the epitaxial layer (comprising 3, 4, 5, and 6) into the epitaxial layer ([0028]), and the well region (4) has a second conductivity type (p-type; [0028]); a drift region (3; [0026]) formed in the epitaxial layer (comprising 3, 4, 5, and 6) and in contact with a bottom surface of the well region (4), wherein the drift region (3) has the first conductivity type (n-type; [0026]); a gate structure (right structure comprising 8 and 9; [0032]) extending downward from the top surface of the epitaxial layer (comprising 3, 4, 5, and 6) to penetrate the well region (4), wherein the gate structure (comprising 8 and 9) is in contact with the drift region (3); a first heavily doped region (6 of right gate structure; [0045]) formed in the well region (4) and positioned on a first side (right side) of the gate structure (right structure comprising 8 and 9), wherein the first heavily doped region (6) has the second conductivity type (p-type; [0044]); a second heavily doped region (5 of right gate structure; [0028]) formed in the well region (4) and positioned on a second side (left side) of the gate structure (right structure comprising 8 and 9), wherein the second side (left side) is opposite to the first side (right side) of the gate structure (right structure comprising 8 and 9), the second heavily doped region (5) has the first conductivity type (n-type; [0028]), and the first conductivity type (n-type) is different from the second conductivity type (p-type); and a contact plug (portion of 11 in direct contact with 5 and 6; [0033]) formed on the epitaxial layer (comprising 3, 4, 5, and 6) and in direct contact with a portion of the first heavily doped region (6) and a portion of the second heavily doped region (5), wherein a gate electrode (9; [0032]) of the gate structure (comprising 8 and 9) is separated from the well region (4) and the drift region (3) by a gate dielectric layer (8; [0032]) of the gate structure (comprising 8 and 9), wherein the gate dielectric layer (8) includes a bottom portion and a sidewall portion (as shown), wherein the first heavily doped region (6) is in direct contact with a portion (upper portion) of the sidewall portion that is adjacent to the first side (right side) of the gate structure (right structure comprising 8 and 9), and wherein the second heavily doped region (5) is in direct contact with another portion (upper portion) of the sidewall portion that is adjacent to the second side (left side) of the gate structure (right structure comprising 8 and 9); [claim 3] wherein a bottom surface of the gate structure (right structure comprising 8 and 9) is separated from the bottom surface of the well region (4) by a first distance (as shown); [claim 13] further comprising: another first heavily doped region (middle 6 between shown left and right gate structures) formed in the well region (4), wherein the another first heavily doped region (middle 6 between shown left and right gate structures) is positioned adjacent to the second heavily doped region (5 of right gate structure) and in direct contact with the second heavily doped region (5 of right gate structure), and wherein the second heavily doped region (5 of right gate structure) is positioned between the another first heavily doped region (middle 6 between shown left and right gate structures) and the gate structure (right structure comprising 8 and 9); [claim 14] further comprising: another gate structure (left structure comprising 8 and 9) adjacent to the gate structure (right structure comprising 8 and 9) and extending downward from the top surface of the epitaxial layer (comprising 3, 4, 5, and 6) to penetrate the well region (4), wherein the another gate structure (left structure comprising 8 and 9) is in contact with the drift region (3), and wherein the another first heavily doped region (middle 6 between shown left and right gate structures) is positioned between the another gate structure (left structure comprising 8 and 9) and the second heavily doped region (5 of right gate structure), and the another first heavily doped region (middle 6 between shown left and right gate structures) is in direct contact with the another gate structure (left structure comprising 8 and 9).
Miyahara fails to expressly disclose [claim 1] a conductive structure formed in the drift region and under the gate structure; wherein the gate electrode is separated from the conductive structure by the gate dielectric layer; [claim 2] wherein a top surface of the conductive structure is lower than the bottom surface of the well region; [claim 3] wherein a bottom surface of the conductive structure is separated from the bottom surface of the well region by a second distance, wherein the second distance is greater than the first distance; [claim 5] wherein a projection area of the gate structure on the substrate overlaps a projection area of the conductive structure on the substrate as viewed from a top side of the well region; [claim 6] wherein a thickness of the bottom portion is greater than a thickness of the sidewall portion, wherein the conductive structure is electrically insulated from the gate electrode by the bottom portion of the gate dielectric layer; [claim 7] further comprising a shielding region formed in the epitaxial layer, wherein the shielding region covers a bottom surface and a portion of lateral surfaces of the conductive structure, and the shielding region has the second conductivity type; and wherein a projection area of the gate structure on the substrate overlaps a projection area of the shielding region on the substrate as viewed from a top side of the well region; [claim 12] wherein a top surface of the conductive structure is lower than a bottom surface of the first heavily doped region, and the top surface of the conductive structure is lower than a bottom surface of the second heavily doped region.
Kobayashi discloses in Fig. 1 [claim 1] a conductive structure (22; [0038]) formed in the drift region (31, which comprises 2 and 3; [0035]) and under the gate structure (comprising 8 and 9; [0035]); wherein the gate electrode (9; [0035]) is separated from the conductive structure (22) by the gate dielectric layer (8a of 8; [0042]); [claim 2] wherein a top surface of the conductive structure (22) is lower than the bottom surface of the well region (4; [0035]); [claim 3] wherein a bottom surface of the conductive structure (22) is separated from the bottom surface of the well region (4) by a second distance, wherein the second distance is greater than the first distance (bottom of well region 4 is separated further from the bottom surface of conductive structure 22 than the bottom surface of gate structure comprising 8 and 9); [claim 5] wherein a projection area of the gate structure (comprising 8 and 9) on the substrate (10; [0035]) overlaps a projection area of the conductive structure (22) on the substrate (10) as viewed from a top side of the well region (4); [claim 6] wherein a thickness (t1; [0045]) of the bottom portion (8a) is greater than a thickness (t2; [0045]) of the sidewall portion (8b), wherein the conductive structure (22) is electrically insulated from the gate electrode (9) by the bottom portion (8a) of the gate dielectric layer (8); [claim 7] further comprising a shielding region (21; [0037]) formed in the epitaxial layer (comprising 31 and 32; [0035]), wherein the shielding region (21) covers a bottom surface (bottommost surface) and a portion of lateral surfaces (rounded side surfaces) of the conductive structure (22), and the shielding region (21) has the second conductivity type (p-type; [0037]); and wherein a projection area of the gate structure (comprising 8 and 9) on the substrate (10) overlaps a projection area of the shielding region (21) on the substrate (10) as viewed from a top side of the well region (4).
As to [claim 12] wherein a top surface of the conductive structure is lower than a bottom surface of the first heavily doped region, and the top surface of the conductive structure is lower than a bottom surface of the second heavily doped region, when the conductive structure 22 of Kobayashi is modified into Miyahara the conductive structure 22 will be at the bottom of the gate structure comprising 8 and 9 of Miyahara such that the bottom surfaces of the first and second heavily doped regions 5 and 6 of Miyahara will be higher than the top surface of the conductive structure 22 with respect to the bottom of the substrate.
Given the teachings of Kobayashi, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Miyahara by employing the well-known or conventional features of SiC transistor fabrication, such as displayed by Kobayashi, by employing a conductive structure that is at the bottom of the gate trench and is separated from the gate electrode by the bottom of the gate dielectric, where the gate dielectric has a greater bottom thickness than side thickness, the conductive structure has a top surface below the bottom surface of the well region and the first and second heavily doped regions, and a shielding structure of the second conductivity type is formed around the bottom and bottom sidewalls of the conductive structure in order to reduce turn-off loss due to the parasitic npn transistor ([0051]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Miyahara in view of Kobayashi as applied to claim 1 above, and further in view of Meiser et al (US 2020/0161437 and Meiser hereinafter).
Although the structure disclosed by Miyahara in view of Kobayashi shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
wherein a width of the gate structure is greater than a width of the conductive structure.
Miyahara in view of Kobayashi discloses a vertical SiC power MOSFET, see [0024].
Meiser discloses a vertical SiC power MOSFET, see Abstract and [0040] wherein a width (Fig. 2; horizontal width at the top of middle 112; [0038]) of the gate structure (comprising 114, 116, and 112; [0038]) is greater (wider) than a width (horizontal width at the bottom of middle 110; [0038]) of the conductive structure (comprising middle 110 where shielding region 130 is formed; [0038]).
Given the teachings of Meiser, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Miyahara in view of Kobayashi by employing the well-known or conventional features of SiC power MOSFET fabrication, such as displayed by Meiser, by employing a gate structure that is wider than the conductive structure in order to provide a device with reduced conduction losses ([0003]).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Miyahara in view of Kobayashi as applied to claim 1 above, and further in view of Hsieh (US 2009/0315106 and Hsieh hereinafter).
As to claim 8: Although the structure disclosed by Miyahara in view of Kobayashi shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
wherein the conductive structure comprises a conductive portion and a metal silicide liner that covers sidewalls and a bottom surface of the conductive portion.
Miyahara in view of Kobayashi discloses that the conductive structure 22 is a trench-SBD, see [0050].
Hsieh discloses a trench-SBD in Fig. 3 wherein the conductive structure (comprising 206 and 222; [0044]) comprises a conductive portion (222; [0044]) and a metal silicide liner (206; [0044]) that covers sidewalls and a bottom surface of the conductive portion (222).
Given the teachings of Hsieh, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Miyahara in view of Kobayashi by employing the well-known or conventional features of trench-SBD fabrication, such as displayed by Hsieh, by employing a metal silicide liner on sidewalls and bottom of a conductive portion of the conductive structure that contacts the shielding region in order to provide a device with reduced resistance ([0014]).
As to claim 9: When the trench-SBD structure of Miyahara in view of Kobayashi is modified to have the materials and structure of Hsieh, the conductive structure 22 of Kobayashi will have wherein the conductive portion (Fig. 3; 222; [0044] of Hsieh) and the metal silicide liner (206; [0044] of Hsieh) are in contact (will be in direct contact) with the gate dielectric layer (Fig. 1; 8a; [0042] of Kobayashi) of the gate structure (Fig. 1; comprising 8 and 9; [0035] of Kobayashi) as Hsieh shows the metal silicide liner only on sidewalls and bottom of the conductive portion. Given the teachings of Hsieh, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Miyahara in view of Kobayashi by employing the well-known or conventional features of trench-SBD fabrication, such as displayed by Hsieh, by employing a metal silicide liner on sidewalls and bottom of a conductive portion of the conductive structure that contacts the shielding region in order to provide a device with reduced resistance ([0014]).
Response to Arguments
Applicant's arguments filed 2/10/2026 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that Kobayashi and Miyahara fail to disclose that the contact plug is formed on the epitaxial layer and in direct contact with a portion of the first and second heavily doped regions. Kobayashi discloses that the source electrode 12a contacts and covers the entire second heavily doped region 5 and the entire first heavily doped region 6. Miyahara discloses through contact holes provided in the interlayer insulating layer 10, but fails to disclose or suggest a contact plug formed on the epitaxial layer and in direct contact with a portion of the first and second heavily doped regions.
Examiner respectfully traverses applicant’s remarks. The primary reference Miyahara expressly shows in Fig. 4 that a portion of the interlayer insulating layer 10 and a portion of the gate dielectric 8 cover a portion of each of the first and second heavily doped regions 6 and 5, respectively. Therefore, Miyahara discloses the claimed limitation of a contact plug (portion of 11 in direct contact with the heavily doped regions 5 and 6 and between adjacent sidewalls of 10) formed on the epitaxial layer (comprising 3 and 4) and in direct contact with a portion of the first (6) and second (5) heavily doped regions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/7/2026