Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 9, 2026 has been entered.
Priority
Acknowledgement is made to claim of priority to Taiwanese application TW111129904, filed August 9, 2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 1-24 are pending in this application.
Applicant elected with traverse of Group I, Species C, (claims 1-11) in the reply filed on June 10, 2025 is acknowledged.
The requirement was deemed proper and is therefore made FINAL in the office action dated August 12, 2025.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed February 9, 2026. Claims 1 and 6-10 are amended. Claims 12-24 remain withdrawn. The Examiner notes that claims 1-11 are examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations “the conductive pillar,” “the first conductive via,” and “the second conductive via” in lines 26, 27, and 29 of claim 1, respectively. There is insufficient antecedent basis for this limitation in the claim as the claim previously recited “a plurality of conductive pillars,” “a plurality of first conductive vias,” and “a plurality of second conductive vias.” The Examiner will consider the limitations to read “a conductive pillar of the plurality of conductive pillars,” “a first conductive via of the plurality of first conductive vias,” and “a second conductive via of the plurality of second conductive vias.”
Dependent claims 2-11 are rejected at least on the same basis as the independent claim upon which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 1 recites “the conductive pillar.” The antecedent basis for the conductive pillar recites “a plurality of conductive pillars.” It is unclear
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2020/0343223 A1) in view of Sung (US 2020/0075542 A1).
With respect to claim 1, Chen teaches in Fig. 7:
An electronic package (package structure PK1F), comprising:
a packaging layer (layer that includes insulating encapsulant 308’ and vias 306);
a stacking component (stacked die unit SU1) embedded in the packaging layer and comprising a first electronic module and a second electronic module stacked on the first electronic module,
wherein the first electronic module (third semiconductor die 30, second protection layer 212, second conductive post 210, and second passivation layer 208, and interconnection layer 204) comprises a first encapsulation layer (second protection layer 212) embedded in the packaging layer (layer that includes 308’),
a first electronic element embedded (30) in the first encapsulation layer (212),
a plurality of first conductive vias (210) embedded in the first encapsulation layer (212),
and at least one first circuit structure (208 and 204) disposed on the first encapsulation layer (212) and electrically connected to the first electronic element (30) and the plurality of first conductive vias (210),
wherein the second electronic module (second semiconductor die 200, first protection layer 112’, first conductive posts 110, first passivation layer 108, and interconnection layer 104) comprises a second encapsulation layer (first protection layer 112’) embedded in the packaging layer (layer that includes 308’),
a second electronic element (200) embedded in the second encapsulation layer (112’), a plurality of second conductive vias (110) embedded in the second encapsulation layer (112’), and at least one second circuit structure (108 and 104) disposed on the second encapsulation layer (112’) and electrically connected to the second electronic element (200) and the plurality of second conductive vias (110),
wherein the plurality of first conductive vias are electrically connected to the plurality of second conductive vias (para. 40 “the redistribution layer RDL2 electrically connects the first conductive posts 110 of the first semiconductor die 100 to the second conductive posts 210 of the second semiconductor die 200”);
a plurality of conductive pillars embedded in the packaging layer (through insulator vias (306);
and a routing structure formed on the packaging layer (redistribution layer RDL2) and electrically connected to the plurality of conductive pillars (306) and the stacking component (SU1),
wherein a height of the packaging layer (308’) is greater than a height of the first encapsulation layer (212) of the first electronic module and a height of the second encapsulation layer (112’) of the second electronic module,
Chen fails to teach:
wherein the second electronic module further comprises a plurality of conductive bumps between the first conductive vias in the first encapsulation layer and the second conductive vias in the second encapsulation layer embedded in the packaging layer,
a height of the packaging layer is greater than a sum of a height of the first encapsulation layer of the first electronic module and a height of the conductive bump and a height of the second encapsulation layer of the second electronic module,
and a height of the conductive pillar in the packaging layer is greater than a sum of a height of the first conductive via in the first encapsulation layer and the height of the conductive bump and a height of the second conductive via in the second encapsulation layer.
Sung teaches a stacked die unit analogous to stacked die unit SU1 of Chen. Second sub-package 200 is analogous to the first electronic module and third sub-package 300 is analogous to the second electronic module. Sung teaches:
wherein the second electronic module (third sub-package 300) further comprises a plurality of conductive bumps (inner connectors 510, which may be conductive bumps, para. 21) between the first conductive vias (through vias 123 and post bumps 125 within sub-package 200) in the first encapsulation layer (second inner molding structure 260 of sub-package 200) and the second conductive vias (through vias 123 and post bumps 125 within sub-package 300) in the second encapsulation layer (inner molding 260 of sub-package 300) embedded in the packaging layer (molding layer 650),
a height of the packaging layer is greater than a sum of a height of the first encapsulation layer of the first electronic module and a height of the conductive bump and a height of the second encapsulation layer of the second electronic module (height of the layer defined by 650 is greater than height of combination of 200 and 300),
Chen teaches that the height of the conductive pillar in the packaging layer extends through the entire height of the packaging layer. Therefore, modifying Chen by the teachings of Sung to use a stacked structure in which all of the dies are wired through a stack of vias connected through a bump teaches:
and a height of the conductive pillar (306 of Chen) in the packaging layer is greater than a sum of a height of the first conductive via (123 and 125 within 200 of Sung) in the first encapsulation layer (200 of Sung) and the height of the conductive bump (510 between 200 and 300 of Sung) and a height of the second conductive via (123 and 125 within 300 of Sung) in the second encapsulation layer (300 of Sung).
Claim 1 is rejected as obvious over Chen and Sung under the rational “Use of Known Technique To Improve Similar Devices (Methods, or Products) in the Same Way” (MPEP 2143(I)(C)). The Graham factual inquires for this rationale are:
(1) a finding that the prior art contained a “base” device (method, or product) upon which the claimed invention can be seen as an “improvement;”
(2) a finding that the prior art contained a “comparable” device (method, or product that is not the same as the base device) that has been improved in the same way as the claimed invention;
(3) a finding that one of ordinary skill in the art could have applied the known “improvement” technique in the same way to the “base” device (method, or product) and the results would have been predictable to one of ordinary skill in the art; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Chen includes a base device of wafer level packaging of a stacked die structure to which the claimed invention can be seen as an improvement because the stacked die structure of the claimed invention includes via structures within different layers that are connected through conductive bumps. Sung teaches a comparable stacked die structure in which the stacked modules include encapsulation layers that each have vias that are connected to each other through conductive bumps, similar to the claimed invention as described above. One of ordinary skill in the art before the effective filing date of the invention could have applied the technique of interconnecting the stacked dies of Sung to the stacked dies within the device of Chen with the predictable result of interconnecting the dies to a lower redistribution layer. The ordinary artisan would be further motivated to make such a modification because the via wiring structure of Sung has a smaller footprint than the wiring structure of Chen and reduces the number of vias laterally next to each other which leads to reduced crosstalk between the vias as taught by para. 40 of Sung.
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363
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With respect to claim 2, Chen further teaches:
wherein a configuration of the first electronic module and a configuration of the second electronic module are the same. (para. 49 “the third semiconductor die 30 may be the same type of semiconductor die as with any one of the first semiconductor die 100 or the second semiconductor die 200, just with different dimensions or sizes.” Also, the configuration of a semiconductor die covered by a passivation structure and interconnection structure surrounded by encapsulation and through vias is the same.)
With respect to claim 3, Chen further teaches: wherein a configuration of the first electronic module and a configuration of the second electronic module are the same. (para. 22 “In another embodiment, the protective material 112 and the second protection layer 212 includes the same materials”)
With respect to claim 4, Chen further teaches:
wherein materials of at least two of the packaging layer, the first encapsulation layer and the second encapsulation layer are the same (Para. 22 “In one embodiment, the protective material 112 (used to form the first protective layer) is different from a material of the second protection layer 212”).
Claims 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2020/0343223 A1) and Sung (US 2020/0075542 A1) as applied to claim 1 above and further in view of Yu (2013/0037950 A1).
With respect to claim 5, Chen/Sung fails to teach:
wherein the at least one first circuit structure is a plurality of first circuit structures respectively disposed on opposing sides of the first encapsulation layer,
and wherein the at least one second circuit structure is a plurality of second circuit structures respectively disposed on opposing sides of the second encapsulation layer.
Yu teaches in Fig. 15:
wherein the at least one first circuit structure is a plurality of first circuit structures respectively disposed on opposing sides of the first encapsulation layer,
and wherein the at least one second circuit structure is a plurality of second circuit structures respectively disposed on opposing sides of the second encapsulation layer. (see annotated Fig. 15 below)
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503
802
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It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of bonding electronic modules of Chen/Sung in which a semiconductor die is directly bonded to exposed vias within a passivation layer for the method of Yu in which the stacked dies are connected by solder bumps and contact pads because they are known equivalents and it would have yielded the predictable result of electrically connecting chips or dies. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 6, Yu further teaches:
wherein one of the plurality of first circuit structures has a plurality of first electrical contact pads (electrical pads on top of chips 3 within 1502),
and the other one of the plurality of first circuit structures has a plurality of first conductive bumps (bumps on bottom side of chip 2 within 1502),
wherein one of the plurality of second circuit structures has the plurality of conductive bumps (bumps on bottom side of chip 2 within 1504),
and the other one of the plurality of second circuit structures has a plurality of second electrical contact pads (pads on top side of chip 3 within 1504),
wherein the second electronic module is disposed onto the plurality of first electrical contact pads of the first electronic module with the plurality of conductive bumps (see annotated Fig. 15, bumps of second circuit structure are connected to pads of first circuit structure).
Yu does not state how the second conductive bumps are attached to the first electrical contact pads. The use of solder material to attach metal bumps to contact pads is well known in the art. It would be obvious to the ordinary artisan to use solder material for the connection. The ordinary artisan would be motivated to modify the teachings of Yu to attach the metal bumps to contact pads to facilitate electrical bonding between the second and third layers.
With respect to claim 7, Yu further teaches:
wherein the stacking component further comprises a bonding material (underfill material 802) covering the plurality of conductive bumps (metal bumps 122 of second circuit structure), the solder material and the first electrical contact pads (pads that make up first circuit structure).
With respect to claim 8, Chen/Sung modified to include the circuit structure and bumps of Yu teaches:
wherein the stacking component further comprises a packaging material (material 308’ of the packaging layer of Chen) covering the plurality of conductive bumps (metal bumps 122 of second circuit structure of Yu), the solder material, the first electrical contact pads (pads that make up first circuit structure of Yu), and the second electronic module (see annotated Fig. 7)
With respect to claim 9, Chen/Sung modified by Yu to include the circuit structures and bumps of Yu teaches:
wherein the stacking component further comprises a bonding material (underfill material 802 of Yu) covering the plurality of conductive bumps (metal bumps 122 of second circuit structure of Yu), the solder material and the first electrical contact pads (pads that make up first circuit structure of Yu),
and a packaging material (material 308’ of the packaging layer of Chen) covering the bonding material (undefill 802 of Yu) and the second electronic module (see annotated Fig. 7)
With respect to claim 10, Chen/Sung fails to teach:
wherein the first circuit structure has a plurality of conductive bumps electrically connected to the routing structure.
Yu teaches in Fig. 15:
wherein the first circuit structure or the second circuit structure has a plurality of conductive bumps electrically connected to the routing structure. (metal bumps 122 of both the first and second circuit structure are connected to the routing structure, see annotated Fig. 15, through the vias and/or chips)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of bonding electronic modules of Chen/Sung in which a semiconductor die is directly bonded to exposed vias within a passivation layer for the method of Yu in which the stacked dies are connected by solder bumps and contact pads because they are known equivalents and it would have yielded the predictable result of electrically connecting chips or dies. Such a modification would result in the claimed subject matter above. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 11, Chen fails to teach:
wherein the first circuit structure or the second circuit structure has a plurality of electrical contact pads electrically connected to the routing structure.
Yu teaches in Fig. 15:
wherein the first circuit structure or the second circuit structure has a plurality of electrical contact pads electrically connected to the routing structure. (contact pads connected to metal bumps 122 in both the first and second circuit structure are connected to the routing structure, see annotated Fig. 15, through the vias and/or chips)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of bonding electronic modules of Chen in which a semiconductor die is directly bonded to exposed vias within a passivation layer for the method of Yu in which the stacked dies are connected by solder bumps and contact pads because they are known equivalents and it would have yielded the predictable result of electrically connecting chips or dies. Such a modification would result in the claimed subject matter above. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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