Prosecution Insights
Last updated: October 01, 2026
Application No. 18/063,787

TRANSISTOR DEVICES INCLUDING SELF-ALIGNED OHMIC CONTACTS AND CONTACT REGIONS AND RELATED FABRICATION METHODS

Non-Final OA §103
Filed
Dec 09, 2022
Examiner
NICELY, JOSEPH C
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
628 granted / 808 resolved
+9.7% vs TC avg
Strong +20% interview lift
Without
With
+19.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
839
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
51.9%
+11.9% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
20.4%
-19.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 808 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office action is in response to the RCE filed 7/10/2026 in which claims 1, 7, 8, and 20 were amended. Claims 1-30 are pending with claims 1-5, 7-13, and 16-18 presented for examination and claims 6, 14, 15, and 19-30 remaining withdrawn. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-5, 7, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sheppard et al (US 2011/0057232 and Sheppard hereinafter) in view of Taniguchi et al (US 2021/0111277 and Taniguchi hereinafter) in view of Hirai et al (US 2016/0260615 and Hirai hereinafter). As to claims 1, 7, 8, and 10: Sheppard discloses [claim 1] a transistor device (Fig. 1D; [0043]), comprising: a semiconductor structure (comprising 20, 22, and 31; [0050]-[0052] and [0067]) comprising an implanted region (31) adjacent a surface (top surface of 22); and a source/drain contact (30; [0083]-[0084]) comprising an ohmic contact portion (30 in contact with 31; [0084]) on the implanted region (31) of the semiconductor structure (comprising 20, 22, and 31), wherein the implanted region (31) laterally extends beyond the ohmic contact portion (30 in contact with 31) by less than about 0.8 microns (distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31, can be about 0.1 to about 0.5 microns, in particular 0.25 microns; [0084]); [claim 7] wherein the semiconductor structure (Fig. 1D; comprising 20, 22, and 31) comprises a channel layer (20) and a barrier layer (22) thereon; [claim 10] wherein: an electrical conduction path (inherently present during device operation) between a channel region (Fig. 1D; region under dielectric 24; [0076]) of the semiconductor structure (comprising 20, 22, and 31) and the source/drain contact (30) comprises a first resistance (inherently there is a resistance in the materials when there is an electrical conduction path) between the semiconductor structure (comprising 20, 22, and 31) and a boundary (outer edge) of the implanted region (31), and a second resistance (inherently there is a resistance in the materials when there is an electrical conduction path) between the implanted region (31) and the ohmic contact portion (30). Sheppard fails to expressly disclose [claim 1] where the semiconductor structure comprises a recess and the implanted region is adjacent a surface of the recess; [claim 7] wherein the recess is in the barrier layer, and wherein the ohmic contact portion of the source/drain contact extends into the recess in the barrier layer. Taniguchi discloses in Fig. 10B a transistor with a semiconductor structure comprising 130, 131, 133, and 135 ([0112]), [claim 1] where the semiconductor structure comprises a recess (recesses are formed in 135 and 133 to expose the layer 131; [0112]) in which the ohmic contact part 121B of the source/drain electrodes 120 are formed; [claim 7] wherein the recess (recesses are formed in 135 and 133 to expose the layer 131) is in the barrier layer (135; [0112]), and wherein the ohmic contact portion (121B; [0112]) of the source/drain contact (comprising 120 and 121B; [0112]) extends into the recess (recesses are formed in 135 and 133 to expose the layer 131) in the barrier layer (135). Therefore, given the teachings of Taniguchi, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Sheppard by employing the well-known or conventional features of HEMT fabrication, such as displayed by Taniguchi, by employing a recess in the barrier layer in which the ohmic contact portion of the source/drain contact is formed to exposed the channel layer in order to further reduce the on-resistance of the transistor ([0113]). As to [claim 1] where the implanted region is adjacent a surface of the recess, when the recess to expose the channel layer as in Taniguchi is modified into Sheppard, the recess will be adjacent to the doped region 31 that will remain that is aligned with layer 24. Sheppard in view of Taniguchi fails to expressly disclose where [claim 1] the source/drain contact laterally extends beyond the implanted region; [claim 8] wherein the source/drain contact further comprises an extension portion laterally extending on the barrier layer. Sheppard shows a square/rectangular cross-section for the source/drain contact 30. Hirai shows in Fig. 1 where the source/drain contacts SE/DE can have a “T”-shaped structure. The “T”-shaped structure of the SE can extend over an isolation region adjacent the source region and can extend over the gate electrode. The “T”-shaped structure of the DE can extend over the isolation region adjacent the drain region. When the “T” shaped SE/DE structures and isolation region of Hirai are modified into Sheppard, the isolation region ISO of Hirai would abut the outer edges of the implanted regions 31 and the “T”-shaped SE/DE structures would have their outer portions overlying the isolation structures such that they extend beyond the implanted region. Further, the “T”-shaped SE would have a field plate extension that extends beyond the implanted region and over the gate electrode. Hirai further discloses [claim 8] wherein the source/drain contact (Fig. 1 of Hirai; SE/DE; [0059]) further comprises an extension portion (portion of SE/DE on top surface of IL1) laterally extending on (“on” is interpreted to mean over as on does not inherently mean in direct contact with; SE/DE are formed on (over) the barrier layer BA and extend laterally toward and away from the gate electrode GE) the barrier layer (BA; [0055]). As to [claim 8] where the extension portion is laterally extending outside the recess and beyond a boundary of the implanted region, when the “T” shaped SE/DE structures and isolation region of Hirai are modified into Sheppard in view of Taniguchi, the isolation region ISO of Hirai would abut the outer edges of the implanted regions 31 and the “T”-shaped SE/DE structures would have their outer portions overlying the isolation structures such that they extend beyond the implanted region. Further, the “T”-shaped SE would have a field plate extension that extends beyond the implanted region and beyond the recess modified into Sheppard by Taniguchi and over the gate electrode. Therefore, given the teachings of Hirai, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Sheppard in view of Taniguchi by employing the well-known or conventional features of HEMT fabrication, such as displayed by Hirai, by employing an isolation region around a HEMT in order to electrically isolate the HEMT from other devices on the substrate and by employing "T" shaped source/drain contacts, such that the contacts have a portion that extend laterally beyond the source/drain (implanted) regions and the source contact extends laterally beyond the implanted region and over the gate electrode in order to improve the breakdown voltage of the device ([0060]). As to where [claim 10] the implanted region is substantially free of a third resistance between the boundary of thereof and an edge of the ohmic contact portion, Sheppard discloses that the implanted regions are doped to a desired concentration, see [0069]. The doping energy and dose are chosen to lower the resistance of the implanted region and to permit fabrication of low resistivity ohmic contacts to the doped region, see [0070]. As Sheppard recognizes that the doping energy and dose are result effective variables, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sheppard’s dosage and energy of the implanted region such that the resistance of the implanted region 30 is lowered as much as possible (to “substantially” zero). One would have chosen the dosage and energy according to a result effective variable desire to reduce the resistance of the implanted region and the contact resistance within the implanted region. As to claims 2 and 3: Sheppard in view of Taniguchi in view of Hirai fail to expressly disclose [claim 2] wherein the implanted region laterally extends less than about 0.2 microns from an edge of the ohmic contact portion; [claim 3] wherein the implanted region laterally extends beyond an edge of the ohmic contact portion by less than about 0.1 microns. Sheppard discloses in [0084] that the distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31, can be about 0.1 to about 0.5 microns. As stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.” Sheppard discloses that the distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31 is set to allow for misalignment tolerances in the formation and patterning of the ohmic metal contact 30 to prevent the metal in 30 from diffusing into dielectric layer 24, whereby a short between the gate contact and the ohmic contacts is prevented ([0084]). Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention to set the distance between the ohmic contacts and the dielectric layer, which is the same distance by which the implanted region 31 extends beyond the edge of the ohmic contact 30, by less than about 0.2 microns and by less than about 0.1 microns, since the claimed ranges and the disclosed range overlap and doing so would involve only routine experimentation, in order to prevent a short between the gate contact and the ohmic contacts while minimizing a distance between the structures ([0084]). As to claim 4: Sheppard in view of Taniguchi in view of Hirai fail to expressly disclose wherein the implanted region laterally extends beyond an edge of the ohmic contact portion by less than about 0.05 microns. Sheppard discloses in [0084] that the distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31, can be about 0.1 to about 0.5 microns. Sheppard discloses that the distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31 is set to allow for misalignment tolerances in the formation and patterning of the ohmic metal contact 30 to prevent the metal in 30 from diffusing into dielectric layer 24, whereby a short between the gate contact and the ohmic contacts is prevented ([0084]). Thus, Sheppard establishes that the distance is a result effective variable. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to set the distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31, to less than about 0.05 microns for the purpose of preventing a short between the gate contact and the ohmic contacts by allowing for misalignment tolerances in formation and patterning of the ohmic metal contact while minimizing the size of the device to allow for more devices to be constructed on the same substrate. As stated in MPEP 2144.05(I), a prima facie case of obviousness exists where the claimed range and the prior art range do not overlap but are close enough that one skilled in the art would have expected them to have the same properties (Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985)). Further, as Sheppard recognizes that the distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31,is a result effective variable, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sheppard’s distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31 to have a distance less than about 0.05 microns, which is slightly smaller than the prior art range of about 0.1 microns. One would have chosen the distance between the closest edge of 30 to 24 and the closest edge of 24 to 30, which corresponds to the part of 31 laterally extending beyond the edge of 30 in contact with 31 according to a result effective variable balancing the need to prevent the ohmic contact and the dielectric from touching but not be so large to defeat the protective purpose of the dielectric layer ([0084]). As to claim 5: Sheppard in view of Taniguchi in view of Hirai fail to expressly disclose wherein an electrical resistance of a lateral extension of the implanted region beyond an edge of the ohmic contact portion is substantially zero. Sheppard discloses that the implanted regions are doped to a desired concentration, see [0069]. The doping energy and dose are chosen to lower the resistance of the implanted region and to permit fabrication of low resistivity ohmic contacts to the doped region, see [0070]. As Sheppard recognizes that the doping energy and dose are result effective variables, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sheppard’s dosage and energy of the implanted region such that the resistance of the implanted region 30 is lowered as much as possible (to “substantially” zero). One would have chosen the dosage and energy according to a result effective variable desire to reduce the resistance of the implanted region and the contact resistance within the implanted region. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sheppard in view of Taniguchi in view of Hirai as applied to claim 1 above, and further in view of Makiyama et al (US 2009/0085063 and Makiyama hereinafter). Although the structure disclosed by Sheppard in view of Taniguchi in view of Hirai shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose: wherein a lateral distance between the source/drain contact and an adjacent source/drain contact is about 3 microns or less, and an on- resistance of the transistor device is less than about 1.7 ohm-millimeters. Makiyama discloses a HEMT where a lateral distance between the source contact and the drain contact (the source/drain contact and an adjacent source/drain contact) is about 2 microns, see [0050] and [0073]. Taniguchi discloses a HEMT with an on-resistance of 0.4 ohm-mm, see [0124]. Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention could have combined all the elements as claimed as all the claimed elements were known in the prior art with no change in their respective functions and the combination would have yielded predictable results, namely employing a contact structure to an implanted region where the distance between the source and drain contacts is within the claimed range such that an on-resistance within the claimed range is provided in order to suppress distortion in a signal ([0011] of Taniguchi) and to provide a HEMT with improved electrical characteristics ([0073] of Makiyama). Allowable Subject Matter Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 12, 13, and 16-18 are allowed over the prior art of record. The following is a statement of reasons for the indication of allowable subject matter: As to claim 12: the closest prior art, Sheppard, discloses a transistor device (Fig. 1D; [0043]), comprising: a semiconductor structure (comprising 20, 22, and 31; [0050]-[0052] and [0067]) comprising a contact region (31) adjacent a surface (top surface of 22) thereof; and a source/drain contact (30; [0083]-[0084]) comprising an ohmic contact portion (30 in contact with 31; [0084]) on the contact region (31) of the semiconductor structure (comprising 20, 22, and 31), a lateral extension (portion of 31 not underneath 30) of the contact region (31) beyond an edge of the ohmic contact portion (30); wherein an electrical conduction path (inherently present during device operation) between a channel region (Fig. 1D; region under dielectric 24; [0076]) of the semiconductor structure (comprising 20, 22, and 31) and the source/drain contact (30) comprises a first resistance (inherently there is a resistance in the materials when there is an electrical conduction path) between the semiconductor structure (comprising 20, 22, and 31) and a boundary (edge) of the contact region (31), a second resistance (inherently there is a resistance in the materials when there is an electrical conduction path) between the contact region (31) and the ohmic contact portion (30), and a third resistance (inherently there is a resistance in the doped region of the implanted region 31 in its entirety) of a lateral extension of the contact region (31) between the boundary (edge) and an edge (right side) of the ohmic contact portion (30). Sheppard fails to expressly disclose where the third resistance is less than the second resistance. As to claim 16: the closest prior art, Sheppard, discloses a transistor device (Fig. 1D; [0043]), comprising: a semiconductor structure (comprising 20, 22, and 31; [0050]-[0052] and [0067]) comprising implanted regions (31) adjacent a surface (top surface of 22) thereof; and source/drain contacts (30; [0083]-[0084]) comprising ohmic contact portions (portions of 30 in direct contact with 31) on the implanted regions (31) of the semiconductor structure (comprising 20, 22, and 31), respectively. Sheppard fails to expressly disclose wherein a lateral distance between the source and drain contacts is about 3 microns or less, an on-resistance of the transistor device is less than about 1.7 ohm-millimeters, and the on-resistance includes a resistance of a lateral extension of the implanted regions beyond the ohmic contact portions. Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant's arguments filed 7/10/2026 have been fully considered but they are not persuasive. In the remarks on pages 11-12, applicant argues in substance that while Hirai discloses a laterally extending (T-shaped) source/drain electrodes SE/DE, the laterally extending horizontal portions of the source/drain electrodes SE/DE do not laterally extend on the barrier layer BA, but rather are spaced apart from the barrier layer BA. Sheppard teaches that the ohmic contact metal 30 should be laterally spaced apart from the dielectric layer 24. If the proposed modification of Sheppard and Hirai based on Sun to provide lateral extensions of the source/drain contacts 30 on the barrier layer 22 and beyond the boundary of the implanted region 31 would result in contact between the source/drain contact 30 and the dielectric layer 24, which is specifically forbidden by Sheppard. Examiner respectfully traverses applicant’s remarks. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., that the source/drain contact should be in direct contact with the barrier layer as implied by the arguments) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The word “on” does not inherently mean -in direct or physical contact with- and does not limit one to the interpretation to mean -in direct or physical contact with-. The broadest reasonable interpretation of the word “on” used by Examiner is that it means -over-, as is well known in the art. Therefore, as Hirai discloses that the source/drain electrodes SE/DE are over (i.e., on) the barrier layer, the claimed limitation is met. Further, the interpretation by Examiner does not require that the source/drain contacts 30 of Sheppard as modified by Taniguchi and Hirai be in direct contact with the dielectric layer 24. Instead, the combination of Taniguchi and Hirai with Sheppard provide for separation of the source/drain electrodes from the dielectric 24 as required by Sheppard. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JOSEPH C. NICELY Primary Examiner Art Unit 2813 /JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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Prosecution Timeline

Dec 09, 2022
Application Filed
Sep 30, 2025
Non-Final Rejection mailed — §103
Dec 30, 2025
Response Filed
Apr 13, 2026
Final Rejection mailed — §103
Jul 10, 2026
Request for Continued Examination
Jul 16, 2026
Response after Non-Final Action
Jul 28, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
98%
With Interview (+19.8%)
2y 4m (~0m remaining)
Median Time to Grant
High
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