DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 10/9/25.
Applicant’s amendment to claim 1 is acknowledged.
Claims 1-13 are pending and subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Regarding claim 1 and the Parvarandeh reference:
Applicant submits that “each of the first conductive structures and the second conductive structures is directly connected between the first electronic module and the second electronic module” because there exists intervening layers such as pad (118) and UBM (122).
This argument is not found persuasive because:
Referring to Applicant’s fig. 2, the conductive structures comprises a plurality of layers. For example, conductive structure (31a) comprises a pad (311) and solder (310). Conductive structure (32a) comprises a pillar (321) and solder (320).
Claim 1 is a “comprising” claim and does not preclude Parvarandeh’s conductive structures to comprise a plurality of layers. With this new interpretation, Parvarandeh teaches amended claim 1 as set forth below.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 2, the limitation “wherein each of the first conductive structures is a solder ball” is indefinite.
Referring to Applicant’s fig. 2, the conductive structure is not just a solder ball because the conductive structure comprises a plurality of layers. For example, conductive structure (31a) comprises a pad (311) and solder (310). Conductive structure (32a) comprises a pillar (321) and solder (320).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parvarandeh et al., US Publication No. 2011/0248398 A1 (of record).
Parvarandeh anticipates (see fig. 6, also see figs. 1-5):
1. An electronic package, comprising:
a first electronic module (114) having a first side and a second side opposing the first side;
a second electronic module (102) stacked on the first side of the first electronic module, wherein an area (e.g. area of 128, 132, 118, 122) between the first side of the first electronic module (114) and the second electronic module (102) is defined as a first interlayer, and an area outward from the second side of the first electronic module is defined as a second interlayer;
a plurality of first conductive structures (132/118/122) having solder material and disposed in the first interlayer; and
a plurality of second conductive structures (128/118/122) having solder material and disposed in the first interlayer, wherein a solder amount of the plurality of first conductive structures (132) is greater than a solder amount of the plurality of second conductive structures (128), wherein each of the first conductive structures (132/118/122) and the second conductive structures (128/118/122) is directly connected between the first electronic module (114) and the second electronic module (102). See Parvarandeh at para. [0001] – [0049], figs. 1-11.
2. The electronic package of claim 1, wherein each of the first conductive structures is a solder ball (e.g. 132 of 132/118/122 is a solder ball)
3. The electronic package of claim 1, wherein each of the second conductive structures (128/118/122) includes a conductive pillar (e.g. 122 replaced with copper pillar 124; See para. [0020] disclosing the UBM 122 can be replaced with a copper pillar 124 as shown in fig. 2) and a solder material (128) formed on an end surface of the conductive pillar.
4. The electronic package of claim 1, wherein the plurality of first conductive structures (132) and the plurality of second conductive structures (128) are configured according to a magnitude of a stress in the first interlayer, such that a stress at positions where the plurality of first conductive structures (132) are distributed in the first interlayer is greater than a stress at positions where the plurality of second conductive structures (128) are distributed in the first interlayer, para. [0025].
5. The electronic package of claim 1, wherein the plurality of first conductive structures (132/118/122) surround the plurality of second conductive structures (128/118/122), figs. 3 and
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parvarandeh, as applied to claim 1 above, in further view of Lin[1] et al., US Publication No. 2017/0243826 A1.
Regarding claim 6:
Parvarandeh teaches all the limitations of claim 1 above, but does not expressly teach the plurality of first conductive structures are further disposed in the second interlayer, and a number of the plurality of first conductive structures in the first interlayer is less than a number of the plurality of first conductive structures in the second interlayer.
In an analogous art, Lin[1] teaches:
(see fig. 4) wherein the plurality of first conductive structures (140) are further disposed in the second interlayer (e.g. below 300/110), and a number of the plurality of first conductive structures (120’) in the first interlayer (e.g. between 300/110 and 700/800/610) is less than a number of the plurality of first conductive structures (140) in the second interlayer. See Lin[1] at para. [0057] – [0058].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Parvarandeh with the teachings of Lin[1] because forming third conductive structures enables the integration of passive components into the electronic package. See Lin[1] at para. [0027], [0053].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parvarandeh, as applied to claim 1 above, in further view of Lin[2] et al., US Publication No. 2018/0165396 A1.
Regarding claim 7: Parvarandeh teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the plurality of second conductive structures are further disposed in the second interlayer, and a number of the plurality of second conductive structures in the first interlayer is greater than a number of the plurality of second conductive structures in the second interlayer.
In an analogous art, Lin[2] teaches:
(see fig. 24) wherein the plurality of second conductive structures (325) are further disposed in the second interlayer (e.g. below 113), and a number of the plurality of second conductive structures (122) in the first interlayer (e.g. above 113) is greater than a number of the plurality of second conductive structures in the second interlayer. See Lin[2] at para. [06530] – [0664].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Parvarandeh with the teachings of Lin[2] because forming the plurality of second conductive structures in the first interlayer to be greater than a number of the plurality of second conductive structures in the second interlayer enables stacking a plurality of semiconductor chips to form a package-on-package (POP) structure. See Lin[2] at para. [0652].
Claim(s) 8, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parvarandeh in view of Lin[1], as applied to claim 1 above, in further view of Ogawa et al., US Publication No. 2005/0258548 A.
Regarding claim 8:
Parvarandeh and Lin[1] teach all the limitations of claim 1 above, and Lin[1] further teaches:
(see fig. 4) further comprising third conductive structures (400, e.g. capacitor) disposed in the first interlayer (e.g. between 300/110 and 700/800/610) and free of having solder. See Lin[1] at para. [0057] – [0058].
Lin[1] does not expressly teach “a plurality of” third conductive structures.
In an analogous art, Ogawa teaches (see fig. 30) a plurality of third conductive structures (3), para. [0005].
Lin[1] further teaches:
12. The electronic package of claim 8, (see fig. 4) wherein the plurality of second conductive structures (640; e.g. lesser amount of solder compared to 120’) surround the plurality of third conductive structures (400), para. [0057] – [0058].
Ogawa teaches a plurality of third conductive structures, as applied to claim 8 above.
Lin[1] further teaches:
13. The electronic package of claim 8, (see fig. 4) wherein the plurality of third conductive structures (500) are further disposed in the second interlayer (e.g. below 300/110), and a number of the plurality of third conductive structures (400) in the first interlayer (e.g. between 300/110 and 700/800/610) is equal to a number of the plurality of third conductive structures (500) in the second interlayer (e.g. below 300/110),
Ogawa teaches a plurality of third conductive structures, as applied to claim 8 above.
Ogawa further teaches (see fig. 30) a number of the plurality of third conductive structures (3 top) in the first interlayer is equal to a number of the plurality of third conductive structures (3 bottom) in the second interlayer, para. [0005]
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Parvarandeh with the teachings of Ogawa because “With advancement of integrated-circuit technology, the operating speed of an IC chip has increased, potentially involving malfunction caused by superposition of noise…” Capacitors can help eliminate the noise. See Ogawa at para. [0005].
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parvarandeh, as applied to claim 1 above, in further view of Zhang et al., CN 110211931 A (see attached English machine translation).
Regarding claims 8-9: Parvarandeh teaches all the limitations of claim 1 above, but does not expressly teach:
further comprising a plurality of third conductive structures disposed in the first interlayer and free of having solder;
wherein each of the third conductive structures includes a first conductive pillar and a second conductive pillar stacked on each other, wherein the first conductive pillar is erected on the first electronic module, and the second conductive pillar is erected on the second electronic module, such that an end surface of the first conductive pillar and an end surface of the second conductive pillar are in contact with each other in the first interlayer.
In an analogous art, Zhang teaches:
(see fig. 5R and labels in fig. 5N) further comprising a plurality of third conductive structures (109/121) disposed in a first interlayer and free of having solder;
wherein each of the third conductive structures (109/121) includes a first conductive pillar (121) and a second conductive pillar (109) stacked on each other. See Zhang at English machine translation page 15.
It would have been obvious to one of ordinary skill in the art to modify Parvarandeh’s fig. 6 with the teachings of Zhang to form conductive pillars between the first electronic module (114) and second electronic module (102) such that “the first conductive pillar (121 of Zhang) is erected on the first electronic module, and the second conductive pillar (109 of Zhang) is erected on the second electronic module, such that an end surface of the first conductive pillar and an end surface of the second conductive pillar are in contact with each other in the first interlayer (e.g. area of 128, 132, 118, 122)” because Zhang “…it can effectively improve the warpage, and obviously improve the radiating performance of the package.” See Zhang at English machine translation page 3.
Claim(s) 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parvarandeh, as applied to claim 1 above, in further view of Li et al., US Publication No. 2017/0278816 A1.
Regarding claims 8 and 11: Parvarandeh teaches all the limitations of claim 1 above, and further teaches:
the plurality of first conductive structures (132/118/122), the plurality of second conductive structures (128/118/122)…are sequentially arranged in a symmetrical manner from outside to inside in the first interlayer (e.g. area of 128, 132, 118, 122), fig. 6.
Parvarandeh does not expressly teach:
further comprising a plurality of third conductive structures disposed in the first interlayer and free of having solder…
… the plurality of third conductive structures are sequentially arranged in a symmetrical manner from outside to inside in the first interlayer.
In an analogous art, Li teaches:
(see fig. 1) further comprising a plurality of third conductive structures (120) disposed in a first interlayer (e.g. above 110) and free of having solder…
wherein the plurality of first conductive structures (135), the plurality of second conductive structures (130) and the plurality of third conductive structures (120) are sequentially arranged in a symmetrical manner from outside to inside in the first interlayer. See Li at para. [0025] – [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Parvarandeh with the teachings of Li because heights of solders and features are varied to accommodate package warpage and account for non-planarity. See Li at para. [0030].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
29 December 2025