DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 3/31/26.
Applicant’s amendment to claims 1, 2, 6 and 7 is acknowledged.
Applicant’s cancellation of claim 5 is acknowledged.
Claims 1-4 and 6-13 are pending and subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US Publication No. 2019/0287877 in view of Parvarandeh et al., US Publication No. 2011/0248398 A1 (of record).
Kim teaches:
An electronic package, comprising (see fig. 7 annotated):
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a first electronic module (20a) having a first side and a second side opposing the first side;
a second electronic module (20b) stacked on the first side of the first electronic module, wherein an area (e.g. area of 40b) between the first side of the first electronic module and the second electronic module is defined as a first interlayer (e.g. first interlayer labeled in fig. 7), and an area (e.g. 40a) outward from the second side of the first electronic module is defined as a second interlayer (e.g. second interlayer labeled in fig. 7);
a plurality of first conductive structures (40b periphery) having solder material and disposed in the first interlayer and the second interlayer; and
a plurality of second conductive structures (40b central) having solder material and disposed in the first interlayer and the second interlayer, … each of the first conductive structures (40b periphery) and the second conductive structures (40b central) is directly connected between the first electronic module (20a) and the second electronic module (20b), the plurality of first conductive structures (40b periphery) disposed in the first interlayer surround the plurality of second conductive structures (40b central) disposed in the first interlayer, and the plurality of first conductive structures (40b periphery) disposed in the second interlayer surround the plurality of second conductive structures (40b central) disposed in the second interlayer. See Kim at para. [0037] – [0041], also see para. [0001] – [0048], figs. 1-9.
Kim does not expressly teach:
wherein a solder amount of the plurality of first conductive structures is greater than a solder amount of the plurality of second conductive structures
In an analogous art, Parvarandeh teaches:
(see fig. 6) wherein a solder amount of the plurality of first conductive structures (132) is greater than a solder amount of the plurality of second conductive structures (128), para. [0026] – [0030].
It would have been obvious to one of ordinary skill in the art to modify Kim with Paravrandeh to form “a solder amount of the plurality of first conductive structures is greater than a solder amount of the plurality of second conductive structures” in order that the bump assemblies can withstand higher levels of stress. See Paravrandeh at Abstract. Also see para. [0025] disclosing “Because the second bump assemblies 132 are larger than the first bump assemblies 128, forces exerted on the solder bumps 116 of the second bump assemblies 132 may be distributed over a larger area…reducing the amount of stress within the solder bumps 116 and decreasing the likelihood that the solder bumps 116 will suffer stress related failure…Consequently, the failure rate of the bump assemblies may be reduced so that the reliability of the wafer-level chip-scale package device 100 is increased.”
Regarding claim 2:
Kim further teaches:
2. The electronic package of claim 1, wherein each of the first conductive structures (40b) comprises a solder ball, fig. 7.
Paravrandeh also teaches:
2. The electronic package of claim 1, wherein each of the first conductive structures (132) comprises a solder ball, fig. 6.
Regarding claim 3:
Paravrandeh further teaches:
3. The electronic package of claim 1, wherein each of the second conductive structures (128/118/122) includes a conductive pillar (e.g. 122 replaced with copper pillar 124; See para. [0020] disclosing the UBM 122 can be replaced with a copper pillar 124 as shown in fig. 2) and a solder material (128) formed on an end surface of the conductive pillar.
Regarding claim 4:
Paravrandeh further teaches:
4. The electronic package of claim 1, wherein the plurality of first conductive structures (132) and the plurality of second conductive structures (128) are configured according to a magnitude of a stress in the first interlayer, such that a stress at positions where the plurality of first conductive structures (132) are distributed in the first interlayer is greater than a stress at positions where the plurality of second conductive structures (128) are distributed in the first interlayer, para. [0025].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of KIm with the teachings of Paravrandeh because the bump assemblies can withstand higher levels of stress. See Paravrandeh at Abstract. Also see para. [0025] disclosing “Because the second bump assemblies 132 are larger than the first bump assemblies 128, forces exerted on the solder bumps 116 of the second bump assemblies 132 may be distributed over a larger area…reducing the amount of stress within the solder bumps 116 and decreasing the likelihood that the solder bumps 116 will suffer stress related failure…Consequently, the failure rate of the bump assemblies may be reduced so that the reliability of the wafer-level chip-scale package device 100 is increased.”
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Parvarandeh, as applied to claim 1 above, in further view of Lin[1] et al., US Publication No. 2017/0243826 A1 (of record).
Regarding claim 6:
Kim and Paravrandeh teach all the limitations of claim 1 above, but do not expressly teach:
wherein a number of the plurality of first conductive structures in the first interlayer is less than a number of the plurality of first conductive structures in the second interlayer.
In an analogous art, Lin[1] teaches:
(see fig. 4) wherein a number of the plurality of first conductive structures (120’) in the first interlayer (e.g. between 300/110 and 700/800/610) is less than a number of the plurality of first conductive structures (140) in the second interlayer. See Lin[1] at para. [0057] – [0058].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Lin[1] to enable the integration of passive components into the electronic package. See Lin[1] at para. [0027], [0053].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Parvarandeh, as applied to claim 1 above, in further view of Lin[2] et al., US Publication No. 2018/0165396 A1 (of record).
Regarding claim 7:
Kim and Paravrandeh teach all the limitations of claim 1 above, but do not expressly teach:
wherein
In an analogous art, Lin[2] teaches:
(see fig. 24) wherein a number of the plurality of second conductive structures (122) in the first interlayer (e.g. above 113) is greater than a number of the plurality of second conductive structures in the second interlayer. See Lin[2] at para. [06530] – [0664].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kim with the teachings of Lin[2] because forming the plurality of second conductive structures in the first interlayer to be greater than a number of the plurality of second conductive structures in the second interlayer enables stacking a plurality of semiconductor chips to form a package-on-package (POP) structure. See Lin[2] at para. [0652].
Claim(s) 8, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Parvarandeh, as applied to claim 1 above, in further view of Lin[1] et al., US Publication No. 2017/0243826 A1 (of record) and Ogawa et al., US Publication No. 2005/0258548 A (of record).
Regarding claim 8:
Kim and Parvarandeh and teach all the limitations of claim 1 above, but do not expressly teach:
further comprising a plurality of third conductive structures disposed in the first interlayer and free of having solder.
In an analogous art, Lin[1] teaches:
(see fig. 4) further comprising third conductive structures (400, e.g. capacitor) disposed in the first interlayer (e.g. between 300/110 and 700/800/610) and free of having solder. See Lin[1] at para. [0057] – [0058].
Lin[1] does not expressly teach “a plurality of” third conductive structures.
In an analogous art, Ogawa teaches (see fig. 30) a plurality of third conductive structures (3), para. [0005].
Lin[1] further teaches:
12. The electronic package of claim 8, (see fig. 4) wherein the plurality of second conductive structures (640; e.g. lesser amount of solder compared to 120’) surround the plurality of third conductive structures (400), para. [0057] – [0058].
Ogawa teaches a plurality of third conductive structures, as applied to claim 8 above.
Lin[1] further teaches:
13. The electronic package of claim 8, (see fig. 4) wherein the plurality of third conductive structures (500) are further disposed in the second interlayer (e.g. below 300/110), and a number of the plurality of third conductive structures (400) in the first interlayer (e.g. between 300/110 and 700/800/610) is equal to a number of the plurality of third conductive structures (500) in the second interlayer (e.g. below 300/110),
Ogawa teaches a plurality of third conductive structures, as applied to claim 8 above.
Ogawa further teaches (see fig. 30) a number of the plurality of third conductive structures (3 top) in the first interlayer is equal to a number of the plurality of third conductive structures (3 bottom) in the second interlayer, para. [0005]
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kim with the teachings of Ogawa because “With advancement of integrated-circuit technology, the operating speed of an IC chip has increased, potentially involving malfunction caused by superposition of noise…” Capacitors can help eliminate the noise. See Ogawa at para. [0005].
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Parvarandeh, as applied to claim 1 above, in further view of Zhang et al., CN 110211931 A (of record, see attached English machine translation).
Regarding claims 8-9: Kim and Parvarandeh teaches all the limitations of claim 1 above, but do not expressly teach:
further comprising a plurality of third conductive structures disposed in the first interlayer and free of having solder;
wherein each of the third conductive structures includes a first conductive pillar and a second conductive pillar stacked on each other, wherein the first conductive pillar is erected on the first electronic module, and the second conductive pillar is erected on the second electronic module, such that an end surface of the first conductive pillar and an end surface of the second conductive pillar are in contact with each other in the first interlayer.
In an analogous art, Zhang teaches:
(see fig. 5R and labels in fig. 5N) further comprising a plurality of third conductive structures (109/121) disposed in a first interlayer and free of having solder;
wherein each of the third conductive structures (109/121) includes a first conductive pillar (121) and a second conductive pillar (109) stacked on each other. See Zhang at English machine translation page 15.
It would have been obvious to one of ordinary skill in the art to modify Kim with the teachings of Zhang to form conductive pillars between the first electronic module (114) and second electronic module (102) such that “the first conductive pillar (121 of Zhang) is erected on the first electronic module, and the second conductive pillar (109 of Zhang) is erected on the second electronic module, such that an end surface of the first conductive pillar and an end surface of the second conductive pillar are in contact with each other in the first interlayer (e.g. area of 128, 132, 118, 122)” because Zhang “…it can effectively improve the warpage, and obviously improve the radiating performance of the package.” See Zhang at English machine translation page 3.
Claim(s) 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Parvarandeh, as applied to claim 1 above, in further view of Li et al., US Publication No. 2017/0278816 A1 (of record).
Regarding claims 8 and 11: Kim and Parvarandeh teach all the limitations of claim 1 above, and Kim further teaches:
the plurality of first conductive structures (40b periphery), the plurality of second conductive structures (40b central)…are sequentially arranged in a symmetrical manner from outside to inside in the first interlayer (e.g. area of 40b; first interlayer labeled in fig. 7)
Kim does not expressly teach:
further comprising a plurality of third conductive structures disposed in the first interlayer and free of having solder…
… the plurality of third conductive structures are sequentially arranged in a symmetrical manner from outside to inside in the first interlayer.
In an analogous art, Li teaches:
(see fig. 1) further comprising a plurality of third conductive structures (120) disposed in a first interlayer (e.g. above 110) and free of having solder…
wherein the plurality of first conductive structures (135), the plurality of second conductive structures (130) and the plurality of third conductive structures (120) are sequentially arranged in a symmetrical manner from outside to inside in the first interlayer. See Li at para. [0025] – [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kim with the teachings of Li because heights of solders and features are varied to accommodate package warpage and account for non-planarity. See Li at para. [0030].
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yim, US 20230042622 A1 (e.g. Yim teaches a package with different solder amounts in fig. 1A.)
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
17 July 2026
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