Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/22/26 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 117 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsueh et al. (U.S. Patent Publication No. 2021/0287994).
Referring to figures 3a-24, Hsueh et al. teaches a semiconductor element comprising:
a semiconductor portion (102);
a nonconductive layer (104b) on the semiconductor portion;
an upper conductive layer (118/120) at least partially embedded in the nonconductive layer (104b), the upper conductive layer formed of a first material (see figures 3E, 5B, 15, 24, paragraphs# 19);
a lower conductive layer (110) embedded in the nonconductive layer (104b), the lower conductive layer (110) below and electrically connected to the upper conductive layer (118/120);
a first barrier layer (112) disposed between the upper conductive layer (120/118) and the lower conductive layer (110), the barrier layer (112) formed of a second material different from the first material, the second material having an electrical resistivity less than 50 x 10° mQ at 20°C and a melting point greater than 1200°C (see paragraphs# 19, 25, figures 3E, 5B, 15, 24, it is noted that the same material has the same resistivity and melting point); and
a second barrier layer (118/310) lining at least a portion of the upper conductive layer (see figures 3E, 5B, 15, 24); and
wherein the second barrier layer (118/310) is disposed between the barrier layer (112) and the upper conductive layer (120, see figures 3E, 5B, 15, 24).
Allowable Subject Matter
Claims 1, 4, 8-9, 12-14, 17, 23, 28, 36-38, 90-91, 93, 95, 98, 121-123 are allowed. None of the prior art teaches a bonding surface comprises a surface of the upper conductive layer opposite the lower conductive layer and a surface of the nonconductive layer, and wherein the bonding surface is configured for hybrid bonding to another element (in claim 1); a bonding surface prepared for hybrid bonding to a second semiconductor element (in claim 90)
Claims 119-120, 124 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. None of the prior art teaches a hybrid bonding surface, the hybrid bonding surface comprising: a nonconductive portion defined by at least a portion of a surface of the nonconductive layer opposite the semiconductor portion; and a conductive portion defined by an exposed surface of the upper conductive layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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