Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4, 8-9, 12-14, 17, 23, 28, 36-38, 90-91, 93, 95, 98, 117-121 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Information Disclosure Statement
The information disclosure statements filed 1/9/26; 12/3/25 have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 90, 93, 95, 98, 121 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 90 recites the limitation "the semiconductor element" in claim 90, line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 8-9, 12-14, 17, 28, 90-91, 93, 95, 117-118 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Hsueh et al. (U.S. Patent Publication No. 2021/0287994).
Referring to figures 3a-24, Hsueh et al. teaches a semiconductor element comprising:
a semiconductor portion (102);
a nonconductive layer (104b) on the semiconductor portion (102);
an upper conductive layer (118/120) at least partially embedded in the nonconductive layer (104b) and having a first lateral width, the upper conductive layer formed of a first material (see paragraph# 19);
a lower conductive layer (110) below and electrically connected to the upper conductive layer (see paragraph# 19), the lower conductive layer (110) comprising a second lateral width greater than the first lateral width (see figure 3E); and
a barrier layer (112, see figure 3E) disposed between the upper conductive layer (120) and the lower conductive layer (110), the barrier layer (112) having a third lateral width greater than the first lateral width (see figure 3E), the barrier layer (112) formed of a second material (Co) different from the first material (cu), the second material having an electrical resistivity less than 50 x 10° mQ at 20°C and a melting point greater than 1200°C (see paragraphs# 19, 25, figure 3E, it is noted that the same material has the same resistivity and melting point).
Regarding to claim 4, wherein the second material comprises at least one of cobalt, tungsten, vanadium, molybdenum, or nickel (see paragraph# 25).
Regarding to claim 8, the electrical resistivity of the second material is in a range of 4.5 x 10% mQ at 20°C to 30 x 10° mQ at 20°C(see paragraph# 25, figure 3E, it is noted that the same material has the same resistivity).
Regarding to claim 9, the melting point of the second material is in a range of 1200°C to 3600°C (see paragraph# 25, figure 3E, it is noted that the same material has the same melting point).
Regarding to claim 12, a second barrier layer (118) at least a portion of the upper conductive layer, the second barrier layer (118) disposed between the barrier layer (112) and the upper conductive layer (118/120, see figure 3E).
Regarding to claim 13, the second barrier layer (118) comprises the second material (see paragraphs# 19, 25).
Regarding to claim 14, the second barrier layer (118) comprises a third material different from the first material and the second material (see paragraphs# 19, 25).
Regarding to claim 17, a thickness of the barrier layer is greater than a thickness of the second barrier layer (see paragraphs# 53, 59, figure 3E).
Regarding to claim 28, the barrier layer (112) is disposed along a length of an upper surface of the lower conductive layer (110), the length being greater than a width of the upper conductive layer (120, see figure 3E).
Regarding to claim 90, a semiconductor element comprising:
a bonding surface prepared for direct bonding to a second semiconductor element (see figure 3E);
a nonconductive portion (104b) having an upper nonconductive surface forming nonconductive portion of the bonding surface (see figure 3E);
a contact structure (118/120) at least partially embedded in the nonconductive portion(104b), the contact structure having an upper contact surface forming conductive portion of the bonding surface of the semiconductor element, the contact structure having a lower side opposite the upper contact surface, the contact structure formed of a first material (see paragraph# 19);
an electrically conductive barrier material (112, see figure 3E) below and electrically connected to the contact structure(120), the electrically conductive barrier material being closer to the lowerside of the contact structure than it is to the upper contact surface of the contact structure, the electrically conductive barrier material comprising a second material (Co) different from the first material (cu), the second material having an electrical resistivity less than 50 x 10° mQ at 20°C and a melting point greater than 1200°C (see paragraphs# 19, 25, figure 3E, it is noted that the same material has the same resistivity and melting point).
Regarding to claim 91, the contact structure (120) comprises copper, and wherein the contact structure comprises less than 20% of the second material (see paragraph# 37, 39, 41, the same material would provide the same properties).
Regarding to claim 93, the second material comprises at least one of cobalt, tungsten, vanadium, or nickel (see paragraph# 25).
Regarding to claim 95, wherein the electrical resistivity of the second material is in a range of 4.5 x 10° mQ at 20°C to 30 x 10% mQ at 20°C, and wherein the melting point of the second material is in a range of 1200°C to 3600°C (see paragraph# 19, 25, the same material would provide the same properties).
Regarding to claim 117, a semiconductor element comprising:
a semiconductor portion (102);
a nonconductive layer (104b) on the semiconductor portion;
an upper conductive layer (118/120) at least partially embedded in the nonconductive layer (104b), the upper conductive layer formed of a first material (see figure 3E, paragraphs# 19);
a lower conductive layer (110) embedded in the nonconductive layer (104b), the lower conductive layer (110) below and electrically connected to the upper conductive layer (118/120);
a first barrier layer (112) disposed between the upper conductive layer (120/118) and the lower conductive layer (110), the barrier layer (112) formed of a second material different from the first material, the second material having an electrical resistivity less than 50 x 10° mQ at 20°C and a melting point greater than 1200°C (see paragraphs# 19, 25, figure 3E, it is noted that the same material has the same resistivity and melting point); and
a second barrier layer (118) lining at least a portion of the upper conductive layer (see figure 3E).
Regarding to claim 118, the second barrier layer (118) is disposed between the barrier layer (112) and the upper conductive layer (120, see figure 3E).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 36-38, 119-121 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsueh et al. (U.S. Patent Publication No. 2021/0287994) applied in claim(s) 1, 4, 8-9, 12-14, 17, 28, 90-91, 93, 95 117-118 above in views of Tsai et al. (U.S. Patent Publication No. 2017/0025381).
Referring to figures 3a-24, Hsueh et al. teaches a semiconductor element comprising:
a semiconductor portion (102);
a nonconductive layer (104b) on the semiconductor portion (102);
an upper conductive layer (118/120) at least partially embedded in the nonconductive layer (104b) and having a first lateral width, the upper conductive layer formed of a first material (see paragraph# 19);
a lower conductive layer (110) below and electrically connected to the upper conductive layer (see paragraph# 19), the lower conductive layer (110) comprising a second lateral width greater than the first lateral width (see figure 3E); and
a barrier layer (112, see figure 3E) disposed between the upper conductive layer (120) and the lower conductive layer (110), the barrier layer (112) having a third lateral width greater than the first lateral width (see figure 3E), the barrier layer (112) formed of a second material (Co) different from the first material (cu), the second material having an electrical resistivity less than 50 x 10° mQ at 20°C and a melting point greater than 1200°C (see paragraphs# 19, 25, figure 3E, it is noted that the same material has the same resistivity and melting point).
However, the reference does not clearly teach a hybrid bonded structure comprising the semiconductor element of claim 1 and a second semiconductor element, an upper nonconductive surface of the semiconductor element directly bonded to a second upper nonconductive surface of the second semiconductor element without an intervening adhesive, an upper contact surface of the upper conductive layer directly bonded to a contact structure of the second semiconductor element (in claims 36, 119-121), forming a second semiconductor element the same structure as the first semiconductor element (in claim 37).
Tsai et al. teaches a hybrid bonded structure comprising the semiconductor element of (202) and a second semiconductor element (204), an upper nonconductive surface (504/222) of the semiconductor element directly bonded to a second upper nonconductive surface (1006) of the second semiconductor element without an intervening adhesive, an upper contact (240) surface of the upper conductive layer directly bonded to a contact structure (238) of the second semiconductor element (see figure 12, in claims 36, 90, 119). It would be obvious to one ordinary skill in the art to form a second semiconductor element similar to the first element
since it is well-known in the art to repeat the same process for multiple effect. See St. Regis paper, Co. V. Bemis Co. Inc. 193 USPQ 8, 11 (7th circuit 1977) (meeting claim 37-38).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed to form a hybrid bonded structure comprising the semiconductor element and a second semiconductor element, an upper nonconductive surface of the semiconductor element directly bonded to a second upper nonconductive surface of the second semiconductor element without an intervening adhesive, an upper contact surface of the upper conductive layer directly bonded to a contact structure of the second semiconductor element in Hsueh et al. as taught by Tsai et al. because it is known in the art to form a die-stacked-on-wafer structure.
Claim 23, 98 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsueh et al. (U.S. Patent Publication No. 2021/0287994) applied in claim(s) 1, 4, 8-9, 12-14, 17, 28, 90-91, 93, 95 117-118 above.
Referring to figures 1-3, Chen et al. teaches a semiconductor element comprising: a semiconductor portion (101/201); a nonconductive layer (208/210/212/214) on the semiconductor portion (201); an upper conductive layer (222) at least partially embedded in a cavity of the nonconductive layer, the upper conductive layer formed of a first material (see paragraph# 37, 41); a lower conductive layer (122) below and electrically connected to the upper conductive layer (see paragraph# 37); and a barrier layer (124a/224a, see figure 3) disposed between the upper conductive layer and the lower conductive layer, the barrier layer laterally wider than the cavity, the barrier layer formed of a second material different from the first material, the second material having an electrical resistivity less than 50 x 10° mQ at 20°C and a melting point greater than 1200°C (see paragraph# 39, 41, figure 3, it is noted that the same material has the same resistivity and melting point).
However, the reference does not clearly teach the specific thickness of the barrier layers and the conductive layers (in claims 17, 23, 98).
The concentration range of claims 17, 23, 98 are considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller, the selection of reaction parameters such as temperature and concentration would have been obvious:
Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed a critical range and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.
In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time the invention was filed would have used any thickness range suitable to the method in process of Hsueh et al. in order to optimize the process.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893