DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The Applicant’s arguments with respect to claims 1, 9 and 16, filed on 01/12/2026, have been carefully considered but are moot in view of new grounds of rejection. The instant Non-Final Rejection replaces the previous Non-Final Rejection mailed on 09/11/2025.
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the conductive feature" in line 13. There is insufficient antecedent basis for this limitation in the claim.
Claims 10-15 are rejected due to their dependency of claim 9.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al. (2019/0319007), hereafter “Uzoh”, and further in view of Chen et al. (US 2018/0151523 A1), hereafter “Chen”.
As to claim 1, Uzoh teaches a method for forming an element, the method comprising:
providing a non-conductive structure (⁋ [0028], Fig. 1, 106);
forming a cavity (⁋ [0032], 112) in the non-conductive structure, the cavity at least partially extends through a thickness of the non-conductive structure from a surface of the non- conductive structure (⁋ [0026], extends from 108);
providing a conductive feature including a first conductive material (⁋ [0028], 110) and a second conductive material (⁋ [0036], 114) over the first conductive material in the cavity, the second conductive material positioned at a bonding surface (108) of the element; and
preparing the bonding surface of the element for direct bonding (⁋ [0031]).
Uzoh fails to teach wherein a maximum grain size of the second conductive material, in a linear lateral dimension, is smaller than 20% of the linear lateral dimension of the conductive feature.
Chen teaches a method for direct bonding wherein a conductive feature (⁋ [0048], Fig. 3, 301+302) has a first conductive material (301) and second conductive material (302), and the maximum grain size of the second conductive feature (⁋ [0049], “below 200 nm”) is smaller than 20% of the linear lateral dimension of the conductive feature (⁋ [0051], “the height H1 is around 10 μm whereas the height H2 is around 8 μm”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the grain size and lateral dimensions taught by Chen into the method of Uzoh because small average grain size in a layer with homogeneous grain size distribution is thus preferred at the bonding interface to promote the grain boundary diffusion and the overall diffusion process (⁋ [0027]).
As o claim 2, Uzoh teaches wherein there are less than 20 parts per million (ppm) of impurities at grain boundaries of the second conductive material (⁋ [0078]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the range of Uzoh because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
As to claim 3, Chen teaches wherein an average grain size of the second conductive material is smaller than an average grain size of the first conductive material (⁋ [0046], Fig. 2A).
As to claim 4, Uzoh teaches wherein the providing the conductive feature comprises separately providing the first conductive material (110) and the second conductive material (114) (⁋ [0036]), and the method further comprising annealing the first conductive material prior to providing the second conductive material (⁋ [0031], “may be intentionally recessed, to allow for material expansion, particularly during heated annealing”.
As to claim 5, Uzoh teaches wherein the providing the conductive material comprises providing the second conductive material over the first conductive material by way of plasma vapor deposition (PVD), or plating at a higher current density than a first deposition process for providing the first conductive material (⁋ [0040]).
As to claim 6, Uzoh and Chen teach the grain size is smaller than the linear lateral dimension of the conductive feature, but does not teach wherein the maximum grain size of the second conductive material is smaller than 10% of the linear lateral dimension of the conductive feature.
On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
As to claim 7, Chen teaches wherein a maximum linear lateral grain size of the second conductive material at the bonding surface is smaller than 200 nm (⁋ [0074], “the average grain size (b) of the copper electroplated after the bonding operation is around 200 to 800 nm”).
As to claim 8, Uzoh teaches wherein a thickness of the second conductive material (114) is less than 50% of a thickness of the conductive feature (110+114) (shown in Fig. 1C, also mentioned in ⁋ [0046]).
As to claim 9, Uzoh teaches a method for forming a bonded structure, the method comprising:
providing a first element (⁋ [0035], 102, “a first die”) including:
a first non-conductive structure (⁋ [0028], Fig. 1, 106) having a non-conductive bonding surface (⁋ [0026], 108),
a cavity (⁋ [0032], 112) extending at least partially through a thickness of the non- conductive structure from the non-conductive bonding surface (extends from 108), and
a first conductive feature disposed in the cavity, having a first conductive material (⁋ [0028], 110) and a second conductive material (⁋ [0036], 114) over the first conductive material, the second conductive material at least partially exposed at a bonding surface of the element;
providing a second element (⁋ [0035], 102, “a second die”) including:
a second non-conductive structure (⁋ [0028], Fig. 1, 106), and
a second conductive feature (⁋⁋ [0028], [0036], 110+116); and
contacting the bonding surface of the first element and a bonding surface of the second element (⁋ [0045]); and
directly bonding the first element and the second element after the contacting (⁋ [0045]).
Uzoh fails to teach wherein a maximum grain size of the second conductive material, in a linear lateral dimension, is smaller than 20% of the linear lateral dimension of the conductive feature and without subjecting the second conductive material to an annealing process.
Chen teaches a method for direct bonding wherein a conductive feature (⁋ [0048], Fig. 3, 301+302) has a first conductive material (301) and second conductive material (302), and the maximum grain size of the second conductive feature (⁋ [0049], “below 200 nm”) is smaller than 20% of the linear lateral dimension of the conductive feature (⁋ [0051], “the height H1 is around 10 μm whereas the height H2 is around 8 μm”), and a second conductive material (109) is not annealed (⁋ [0075], Fig. 10C).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the grain size and lateral dimensions taught by Chen into the method of Uzoh because small average grain size in a layer with homogeneous grain size distribution is thus preferred at the bonding interface to promote the grain boundary diffusion and the overall diffusion process (⁋ [0027]). Additionally, not annealing the second conductive material will decrease the average grain size (⁋ [0075]).
As to claim 10, Uzoh teaches wherein there are less than 20 parts per million (ppm) of impurities at grain boundaries of the second conductive material (⁋ [0078]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the range of Uzoh because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
As to claim 11, Uzoh teaches wherein the directly bonding the first element and the second element comprises directly bonding the first non-conductive structure and the second non-conductive structure without an intervening adhesive (⁋⁋ [0045]-[0046]), and directly bonding the first conductive feature and the second conductive feature without an intervening adhesive (⁋⁋ [0045]-[0046]).
As to claim 12, Uzoh teaches wherein the providing the first element comprises: providing the first non-conductive structure (106); forming the cavity (112) in the first non-conductive structure; providing a first conductive material (110); providing a second conductive material (114) after providing the first conductive material; and annealing the first conductive material prior to providing the second conductive material (⁋ [0031]).
As to claim 14, Chen teaches wherein a maximum grain size of the second conductive material, in a linear lateral dimension, after directly bonding the first element and the second element is smaller than 30% of the linear lateral dimension of the conductive feature (⁋ [0074], “the average grain size (a) is 1.5 to 5 times greater than the average grain size (b) in said embodiments”).
As to claim 15, Chen teaches wherein a maximum linear lateral grain size of the second conductive material at the bonding surface after directly bonding the first element and the second element is smaller than 2 µm (⁋ [0074], “and the average grain size (b) of the copper electroplated after the bonding operation is around 200 to 800 nm”).
Claims 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, and further in view of Uzoh (US 2020/0194396 A1), hereafter “Uzoh ‘396”.
As to claim 16, Chen teaches a method of forming a conductive feature in a substrate for direct hybrid bonding, the method comprising:
depositing a first conductive material (⁋ [0071], 107, Fig. 10B) by a first deposition process comprising plating (“electroplating operation”) under conditions (“2.5 A constant current for 1600 seconds”) for forming a first average grain size;
depositing a second conductive material (⁋ [0072], 109, Fig. 10C) by a second deposition process different from the first deposition process (“at 7 A constant current for 120 seconds”), wherein the second deposition process forms a second average grain size smaller than the first deposition process (⁋ [0074], “the average grain size (a) is 1.5 to 5 times greater than the average grain size (b) in said embodiments”).
The embodiment of Chen related to Figs. 10A to Fig. 10D fails to teach without increasing impurity levels relative to the first deposition process, wherein a maximum grain size of the second conductive material, in a linear lateral dimension, is smaller than 20% of the linear lateral dimension of the conductive feature, and preparing a bonding surface including the second conductive material and a nonconductive surface for direct hybrid bonding.
Chen further teaches an embodiment related to Fig. 3 which teaches a method for direct bonding wherein a conductive feature (⁋ [0048], Fig. 3, 301+302) has a first conductive material (301) and second conductive material (302), and the maximum grain size of the second conductive feature (⁋ [0049], “below 200 nm”) is smaller than 20% of the linear lateral dimension of the conductive feature (⁋ [0051], “the height H1 is around 10 μm whereas the height H2 is around 8 μm”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the grain size and lateral dimensions taught by Chen’s Fig. 3 embodiment into the method of Chen’s Fig. 10 embodiment because small average grain size in a layer with homogeneous grain size distribution is thus preferred at the bonding interface to promote the grain boundary diffusion and the overall diffusion process (⁋ [0027]).
Chen fails to teach without increasing impurity levels relative to the first deposition process, and preparing a bonding surface including the second conductive material and a nonconductive surface for direct hybrid bonding.
Uzoh ‘396 teaches a method for direct hybrid bonding (⁋ [0035]) wherein the concentration of impurities within a conductive layer can influence surface mobility of the atoms at the bonding surface (⁋ [0024]) and a bonding surface (⁋ [0047], 108) is prepared for bonding including nonconductive surface (106) and conductive material (110) (⁋ [0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the concentration of impurity teaching and bonding surface preparation of Uzoh ’396 within both embodiment’s of Chen because greater surface mobility or faster moving atoms at one or both of the bonding surfaces can result in reliable bonds between conductive interconnect structures at comparatively lower temperatures (⁋ [0024]) and provide the flat, smooth surface that results in a reliable bond (⁋ [0047]).
As to claim 18, Chen teaches wherein the second deposition process is a process that suppresses grain growth (⁋ [0074], “the average grain size (a) is 1.5 to 5 times greater than the average grain size (b) in said embodiments”) and Uzoh ‘369 teaches without introducing less than 20 parts per million (ppm) of impurities at grain boundaries of the second conductive material (⁋ [0059], “preferably below 15 ppm).
As to claim 19, Chen teaches wherein the first deposition process comprises a plating process (see claim 1).
Chen fails to teach and the second deposition process comprises a vapor deposition process but instead teaches the second deposition process as a plating process.
Uzoh teaches a similar bonding technique wherein the second deposition process of fill layer 114 can be completed by may be selectively electrolessly plated, vapor coated, or deposited by atomic layer deposition methods (or the like) (⁋ [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the vapor deposition process of Uzoh for the plating process of Chen since it was already well known in the art that the two processes are interchangeable.
As to claim 20, Chen teaches wherein the first deposition process comprises plating using a first current density and the second deposition process comprises plating using a second current density higher than the first current density (see claim 1).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh, Chen, and further in view of Lien et al. (US 2023/0120352 A1), hereafter “Lien”.
As to claim 13, Uzoh and Chen fail to teach wherein an entire exposed area of the conductive feature is smaller than 7 µm2.
Lien teaches a Cu-to-Cu bonding process wherein the bond pads may be about 5 µm2 (⁋ [0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the exposed area of Lien because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Uzoh ‘396, and further in view of Vreeland et al. (US 2021/0098359 A1), hereafter “Vreeland”.
As to claim 17, Uzoh ‘396 and Chen fails to teach wherein an impurity level of the first conductive material being equal to or greater than the second conductive material.
Vreeland teaches a conductive feature comprised of a first conductive material (⁋ [0040], 222, Fig. 4) and second conductive material (⁋ [0048], 230), wherein the impurity level of 222 is higher than 230 (⁋ [0049], “augmentation metal 230 is higher purity (e.g., Cu) than fill metal 222”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the difference in impurity levels of Vreeland into the method of Uzoh ‘396 and Chen to at least partially backfill a recess or “dish” in a surface of the metallization feature resulting from a planarization process (⁋ [0034]).
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893