Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 12/16/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 21-23,30 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Giacomini et al. (Giacomini, G. et al, “Fabrication and electrical characterization of High-Voltage silicon JFETs”, Journal of Instrumentation, Institute of Physics Publishing, Bristol, GB, vol. 14, no. 5, May 8, 2019, 15 pages), hereinafter referred to as “Giacomini”.
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Regarding claim 21, Giacomini discloses a method of making a Junction Field Effect Transistor (JFET) semiconductor device, comprising:
providing a substrate (with drift region on drain as shown) including a drain region of the JFET semiconductor device;
providing a drift region (shown above) on the substrate;
providing a lower gate (bottom gate) on the drift region;
providing a source region (shown above) having a lower source region (beside channel) that is disposed on the lower gate and extends laterally beyond the lower gate, and an upper source region disposed on the lower source region; and
providing an upper gate (top gate) formed on the lower source region and at least partially surrounding the upper source region, and extending laterally beyond the lower gate to define a gate offset (lateral distance between the edges of bottom gate and top gate) between the upper gate and the lower gate.
Regarding claim 22, Giacomini discloses further comprising: providing a gate contact region that is in contact with the upper gate and the lower gate to provide a common gate contact for the JFET semiconductor device (Pg 2, 3rd para).
Regarding claim 23, Giacomini discloses wherein a channel length of the JFET semiconductor device is defined in the lower source region as an overlap of an outer edge of the lower gate and an inner edge of the upper gate (from figure above).
Regarding claim 30, Giacomini discloses wherein the JFET semiconductor device is normally on (Page 1, line 18).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giacomini as applied to claim 21 above in view of US 20230098516 A1 (Pala).
Regarding claim 28, Giacomini shows the substrate and the drift region.
Giacomini does not show wherein the substrate and the drift region comprise Silicon Carbide (SiC).
Pala shows (Fig. 2) wherein the substrate and the drift region comprise Silicon Carbide (SiC) (para 71).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Pala, with material for substrate and drift, to the invention of Giacomini.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the substrate and drift material made of SiC, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
2. Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giacomini as applied to claim 21 above in view of US 20080230812 A1 (Disney).
Regarding claim 29, Giacomini shows the gate offset.
Giacomini does not show wherein the gate offset is 0.05 microns or less.
Disney shows (Fig. 4) wherein the gate offset is 1-20 microns (para 54) which overlaps the claimed range.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate overlap width of the JFET device of Giacomini with the range of upper gate lengths (corresponding with gate overlap widths) of Disney to easily turn off the JFET device through biasing the gates (see Disney [0053]); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the range of gate overlap widths for the JFET device of Giacomini (Giacomini Figure 1 and Figure 3(d); Giacomini page 4, lines 1-4) with the range of gate overlap width described in Disney (Disney [0054] and Disney Figure 4) to obtain predictable results (see Disney [0053]).
3. Claim(s) 31-32,35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giacomini in view of US 20180122931 A1 (Siemieniec).
Regarding claim 31, Giacomini discloses a method of making a Junction Field Effect Transistor (JFET) semiconductor device, comprising:
providing a substrate (shown above) including a drain region (shown above) of the JFET semiconductor device;
providing a drift region (shown above) on the substrate; and
for each unit cell:
providing a lower gate (bottom gate) on the drift region;
providing a source region (shown above) having a lower source region that is disposed on the lower gate (shown above) and extends laterally beyond the lower gate, and an upper source region disposed on the lower source region; and
providing an upper gate (top gate as shown) formed on the lower source region and at least partially surrounding the upper source region, and extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.
Giacomini does not show a plurality of unit cells on the drift region in a grid.
Siemieniec shows (Fig. 8) a plurality of unit cells on the drift region (11, para 38) in a grid (para 38).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Siemieniec, with plurality of unit cells, to the invention of Giacomini.
The motivation to do so is that the combination produces the predictable result of having more power delivered with high current rating (para 4).
Regarding claim 32, Giacomini as previously modified with Siemieniec shows wherein a pitch of the JFET semiconductor device defined between adjacent unit cells is 5 microns or less (Siemieniec, para 35, 2 micron pitch).
Regarding claim 35, Giacomini as previously modified with Siemieniec discloses further comprising: providing each unit cell with a gate contact region that is in contact with the upper gate and the lower gate to provide a common gate contact for the JFET semiconductor device (Giacomini, Pg 2, ln 20-22, intermediate gate to connect the top and bottom gate).
4. Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giacomini in view of Siemieniec as applied to claim 31 above, further in view of Disney.
Regarding claim 34, Giacomini in view of Siemieniec shows the gate offset.
Giacomini in view of Siemieniec does not show wherein the gate offset is 0.05 microns or less.
Disney shows (Fig. 4) wherein the gate offset is 1-20 microns (para 54) which overlaps the claimed range.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate overlap width of the JFET device of Giacomini with the range of upper gate lengths (corresponding with gate overlap widths) of Disney to easily turn off the JFET device through biasing the gates (see Disney [0053]); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the range of gate overlap widths for the JFET device of Giacomini (Giacomini Figure 1 and Figure 3(d); Giacomini page 4, lines 1-4) with the range of gate overlap width described in Disney (Disney [0054] and Disney Figure 4) to obtain predictable results (see Disney [0053]).
Allowable Subject Matter
Claims 16-20 are allowed.
Regarding claim 16, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a second spacer on the first spacer to define a third opening that is smaller than the second opening” when taken in combination with all the remaining limitations of the independent claim.
Claims 24-27 and 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 24, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming the gate contact region partially overlapped with the upper gate by a distance that is less than the channel length”.
Regarding claim 25, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming the gate contact region partially overlapped with the lower source region”.
Regarding claim 26, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “gate-source breakdown voltage (BVgs) enhancing region on the lower source region and disposed between the upper source region and the upper gate”.
Regarding claim 33, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein each unit cell includes a gate-source breakdown voltage (BVgs) enhancing region formed on the lower source region and between the upper source region and the upper gate”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812