DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters “18” and “16” have both been used to designate the semiconductor material 16 in figs. 2A, 2B, 2C, & 2D. Furthermore, reference characters “26” and “30” have both been used to designate the interlevel dielectric material 30 in fig. 1. Furthermore, reference characters “22’ and “28” have both been used to designate the mask 38 in fig. 1. Additionally, regarding layer 38, the layer is shown as being disposed in a recess of layer 16 when no such process is described; see fig. 2B. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because the shading used therein does not clearly separate the layers depicted. For example, in figs. 1-2B, the layer 38 extends over the gate structure but also under it. This depiction is not in line with the specification wherein the layer 38 is taught as being selectively deposited, see [0026]. Additionally, element 24 in shown in fig. 2D as floating off the edge of the gate structure. This would not occur if element 24 was deposited through conventional deposition processes, as the specification indicates, see [0029]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
Applicant's arguments filed 8/6/2025 have been fully considered but they are not persuasive. The Applicant asserts that by using two separate layers of the Lee reference, the Examiner has mischaracterized the reference. This assertion is not keeping with the broadest reasonable interpretation of the references cited. Multiple layers may make up a channel region, even if Lee does not say so. The Applicant further argues that the 2DEG layer 120 is the only layer of Lee that can be considered a channel region. This argument is not convincing because the broadest reasonable interpretation of “channel” and “region” may be an area including a channel layer, the rejection previously of record and the below following this interpretation. In other words, the rejection of claims 1, 11, & 20 is appropriate for the current scope of the claims because they are broad enough to allow for this interpretation.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5-7, 10, 13, 15, & 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The cited claims above each recite the term “gate dielectric.” From a reading of the specification, it seems that the layer being referenced may be element 24, which is explicitly described as comprising a passivation material. It is not clear if element 24 can be a gate dielectric, in light of the specification. Correction is required. For the purposes of compact prosecution, the term “gate dielectric” is interpreted as “dielectric.” The Applicant will note that the Examiner has not changed the claims to recite “dielectric” only, but is noting the Examiner’s interpretation thereof.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 has been amended in a curative manner, the 112 (b) rejection of claim 10 is withdrawn.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the gate dielectric material" in ln. 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of compact prosecution, this phrase is interpreted as “a gate dielectric material.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, & 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20170077282 A1 to Lee et al. (hereinafter “Lee”).
Regarding claim 1, Lee teaches A structure (structure of fig. 2B) [0043] comprising:
a gate structure (structure comprising gate electrode GE, source electrode SE, and drain electrode DE, and portion of semiconductor layer 115 hereinafter “gate structure”; fig. 2B) [0028], [0030], & [0043]; and
a channel region (2-dimensional electron gas region 120 and semiconductor layer 110, hereinafter “channel region”; fig. 2B) [0029] under the gate structure (GE), the channel region (120) comprising a first portion (portion of channel region directly below gate structure GE, hereinafter “first portion”) comprising a first thickness (annotated below, hereinafter “first thickness”) and a second portion (portion not beneath gate electrode GE, hereinafter “second portion”) comprising a second thickness (annotated below, hereinafter “second thickness”) greater than the first thickness (first thickness), the second portion (second portion) being positioned remotely (separately) from the gate structure (GE).
PNG
media_image1.png
486
676
media_image1.png
Greyscale
Fig. 2B from Lee
Regarding claim 10, Lee teaches the structure of claim 1, wherein the second portion (assumed to be a portion within the second thickness; fig. 2B) extends over (vertically overlapping) a drain region (region wherein drain electrode DE is disposed) of the gate structure (gate structure) and further comprising a gate dielectric material (130P) [0032] directly contacting the first portion (first portion) and the second portion (second portion), and a field plate (140) directly contacting the gate dielectric material over the first portion (first portion) and the second portion (second portion), wherein underneath the gate structure (gate structure) is devoid of the gate dielectric material (130P).
Regarding claim 11, Lee teaches A structure comprising: a gate structure (a structure comprising gate electrode GE, source electrode SE, and drain electrode DE, hereinafter “gate structure”; fig. 2B) [0030] & [0043] comprising GaN (meaning any part of the gate structure may comprise GaN) (semiconductor layer 110 comprises GaN) [0029];
a channel region (2-dimensional electron gas region 120 and semiconductor layer 110, hereinafter “channel region”; fig. 2B) [0029] comprising semiconductor material (material of 110) [0029] under the gate structure (gate structure), the semiconductor material having a different thickness (first thickness and second thickness defined in the annotated fig.) under the gate structure (gate structure) than adjacent a drain region (region including the drain electrode DE; fig. 2B) [0039] of the gate structure (gate structure); and a field plate (140; fig. 2B) over the semiconductor material (material of 110).
PNG
media_image1.png
486
676
media_image1.png
Greyscale
Fig. 2B from Lee
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 8, 12, 13, 15, & 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Enhanced performance of GaN-based light emitting diode with isoelectronic Al doping layer to Jae-Hoon Lee et al. (hereinafter “Jae-Hoon”).
Regarding claim 2, Lee does not teach the structure of claim 1, wherein the channel region (channel region) comprises AlGaN. Lee teaches that the channel region may be comprised of GaN [0029].
Jae-Hoon, however, teaches that doping a GaN layer with aluminum increase electron mobility (abstract).
It would have been obvious to the POSITA before the effective filing date of the invention, to dope the channel layer of Lee with aluminum (thus forming a AlGaN layer) to increase electron mobility as taught by Jae-Hoon in the abstract.
Regarding claim 8, Lee in view of Jae-Hoon, as presently modified, does not teach the structure of claim 2, wherein the second thickness comprises an Al concentration different at a top surface than a bottom surface.
Jae-Hoon, however, teaches a GaN layer with a different Al concentration at the top surface than the bottom surface (figs. 1 & 2) (III results and discussion).
It would have been obvious to the POSITA to dispose the Al dopant with different concentrations at different depths to control certain attributes of the device as taught by Jae-Hoon (III results and discussion).
Regarding claim 12, Lee does not teach the structure of claim 11, wherein the semiconductor material (material of 110) comprises AlGaN. Lee teaches that 110 comprises GaN but is silent on aluminum being a dopant thereof.
Jae-Hoon, however, teaches that doping a GaN layer with aluminum increase electron mobility (abstract).
It would have been obvious to the POSITA before the effective filing date of the invention, to dope the channel layer of Lee with aluminum (thus forming a AlGaN layer) to increase electron mobility as taught by Jae-Hoon in the abstract.
Regarding claim 13, Lee in view of Jae-Hoon teaches the structure of claim 12 further comprising a stepped region (area where the thickness changes between the portions with different thicknesses, hereinafter “stepped region”; see fig. 2B) between the different thickness of the semiconductor material (material of 110), the stepped region (stepped region) being positioned away (to or at a distance from a thing) from the gate structure (gate structure) and a gate dielectric material (125 and 130P) directly contacting the stepped region (stepped region), the semiconductor material (110) of the channel region (channel region) with the different thickness and a top surface of the gate structure (gate structure). To further clarify, the term ‘away’ is interpreted as something being positioned at a distance from a thing. The term ‘away’ does not define what distance or how much distance. Because the drawings filed in an application are not to scale, unless specified by the author, which Lee does not give any such specification, Lee reads on the limitation of ‘away’ in this context. M.P.E.P. 2125 II.
Regarding claim 15, Lee in view of Jae-Hoon teaches the structure of claim 12, wherein the field plate (140) comprises metal material [0038] extending over the different thickness (portions of different thicknesses, specifically the first and second thickness) of the semiconductor material (material of 110) with a gate dielectric material (125 and portion of 130P) between and directly contacting both the field plate (140) and the different thickness of the semiconductor material (110) of the channel region (channel region).
Regarding claim 16, Lee in view of Jae-Hoon teaches the structure of claim 15, wherein the gate dielectric material (125 and portion of 130P) is between the field plate (140) and the semiconductor material (110) and also extends to and is in direct contact with a top surface of a conductive material of the gate structure (gate structure).
Regarding claim 17, Lee in view of Jae-Hoon teaches the structure of claim 12, wherein the semiconductor material comprises a first thickness (first thickness indicated in annotated fig. above) and a second thickness (second thickness indicated in the annotated fig. above), the second thickness (second thickness) being greater than the first thickness (first thickness) and being separated from the gate structure (gate structure), and the gate structure (gate structure) directly contacts the semiconductor material of the first thickness (first thickness) and is remote from the semiconductor material of the second thickness (second thickness). To further clarify, at least a portion of the second thickness is separated from the gate structure in that it does not appear to be close to the gate structure, such as at the midpoint of the second thickness between the gate electrode GE and the drain electrode DE.
Regarding claim 18, Lee in view of Jae-Hoon, as presently modified, does not teach the structure of claim 17, wherein the second thickness comprises an Al concentration different at a top surface than a bottom surface.
Jae-Hoon, however, teaches a GaN layer with a different Al concentration at the top surface than the bottom surface (figs. 1 & 2) (III results and discussion).
It would have been obvious to the POSITA to dispose the Al dopant with different concentrations at different depths to control certain attributes of the device as taught by Jae-Hoon (III results and discussion).
Claims 3-4, 6-7, & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jae-Hoon as applied to claims 2 and 12 above, and further in view of On the physical operation and optimization of the p-GaN gate in normally-off GaN HEMT devices to Efthymiou et al. (hereinafter “Efthymiou”).
Regarding claim 3, Lee in view of Jae-Hoon does not teach the structure of claim 2, wherein the gate structure (gate structure) comprises pGaN.
Efthymiou, however, teaches a HEMT device (fig. 1) comprising a pGaN gate structure (fig. 1). It would have been obvious to the POSITA before the effective filing date of the invention, to modify the gate structure of Lee to comprise pGaN to allow for control over some properties of the device such as threshold voltage as taught by Efthymiou (p. 2 left col.).
Regarding claim 4, Lee in view of Jae-Hoon and Efthymiou teaches the structure of claim 3, wherein a junction (area where the thickness changes) between the first portion (first portion) and the second portion (second portion) comprises a stepped portion (area where the thickness changes between the first portion and second portion, hereinafter “stepped portion”; see fig. 2B).
Regarding claim 6, Lee in view of Jae-Hoon and Efthymiou teaches the structure of claim 4, further comprising a field plate (140; fig. 2B) [0033] that extends over the first portion (first portion), second portion (second portion) and the stepped portion (stepped portion) wherein a gate dielectric material (125 and portions of 130P; fig. 2B) [0031] is directly contacting a surface of the first portion (first portion), the second portion (second portion), the stepped portion (stepped portion) and a top surface of a conductive material of the gate structure (gate structure).
Regarding claim 7, Lee in view of Jae-Hoon and Efthymiou teaches the structure of claim 6, wherein the gate dielectric material (125 and 130P) is between the field plate (140) and both the first portion (first portion) and the second portion (second portion), and a semiconductor material (115) of the gate structure (gate structure) directly contacts the channel region (channel region) on the first thickness.
Regarding claim 14, Lee in view of Jae-Hoon and Efthymiou, as presently modified, does not teach the structure of claim 12, wherein the gate structure comprises pGaN.
Efthymiou, however, teaches a HEMT device (fig. 1) comprising a pGaN gate structure (fig. 1).
It would have been obvious to the POSITA before the effective filing date of the invention, to modify the gate structure of Lee to comprise pGaN to allow for control over some properties of the device such as threshold voltage as taught by Efthymiou (p. 2 left col.).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jae-Hoon and Efthymiou as applied to claim 4 above, and further in view of U.S. Pat. Pub. No. US 20190280093 A1 to Curatola et al. (hereinafter “Curatola”).
Regarding claim 5, Lee teaches the structure of claim 4, further comprising a gate dielectric material (125; fig. 2B) [0031] directly contacting a surface of the stepped portion.
Regarding claim 5, Lee does not teach the structure of claim 4, wherein the stepped portion (stepped portion) is remote from the gate structure.
Curatola, however, teaches an HEMT (abstract; fig. 3) wherein the stepped portion (142; fig. 3) [0039] is remote from the gate structure (122; fig. 3) [0027].
It would have been obvious to the POSITA before the effective filing date of the invention, to modify the stepped portion of Lee to be remote from the gate structure to control some of the properties of the device such as carrier density as well as threshold voltage and drain-source resistance as taught by Curatola [0041].
Claims 9 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Curalota.
Regarding claim 9, Lee does not teach the structure of claim 1, wherein the second portion (second portion) is twice as thick as the first portion (first portion). Lee is silent in this regard.
Curalota, however, teaches that some properties of the device (e.g., carrier density, threshold voltage, and drain-source resistance) [0041] may be modified as it relates to thickness (i.e., positioning of components as well as thicknesses of the layers where they are disposed) [0041].
It would have been obvious to the POSTIA before the effective filing date of the invention, to modify the thicknesses of the first and second portions because Curalota establishes the prior art conditions in para [0041] necessary for the POSITA to modify the thickness of the first and second portions with a reasonable expectation of success. Arriving at a ratio of thicknesses between the first and second portions would have otherwise been a matter of routine optimization. M.P.E.P. 2144.05 II (A).
Regarding claim 20, Lee teaches a method comprising: forming a gate structure (structure comprising gate electrode GE, source electrode SE, and drain electrode DE, hereinafter “gate structure”; fig. 2B) [0030 & [0043]; and forming a channel region (2-dimensional electron gas region 120 and semiconductor layer 110, hereinafter “channel region”; fig. 1B) [0029] under the gate structure (gate structure), the channel region (channel region) comprising a first portion (portion of channel region directly below gate electrode GE, hereinafter “first portion”) comprising a first thickness (first thickness as annotated below) and a second portion (portion not beneath gate electrode GE, hereinafter “second portion”) comprising a second thickness (second thickness as annotated below) greater than the first thickness (first thickness), the second portion (second portion)
Lee does not teach that the second portion is positioned remotely from the gate structure.
Curatola, however, teaches an HEMT (abstract; fig. 3) wherein the second portion (138; fig. 3) [0038] is remote from the gate structure (122; fig. 3) [0027].
It would have been obvious to the POSITA before the effective filing date of the invention, to modify the second portion of Lee to be remote from the gate structure to control some of the properties of the device such as carrier density as well as threshold voltage and drain-source resistance as taught by Curatola [0041].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jae-Hoon and Curalota.
Regarding claim 19, Lee in view of Jae-Hoon teaches the structure of claim 17. wherein the second thickness (second thickness) extends over the drain region (region including DE) of the gate structure (gate structure) and the field plate (140) extends over the first thickness (first thickness) and the second thickness (second thickness) of the semiconductor material (material of 110).
Lee in view of Jae-Hoon does not teach that the field plate is in direct contact with the semiconductor material.
Curatola, however, teaches a field plate (120; fig. 3) in direct contact with the semiconductor material (128; fig. 3) on the first and second thicknesses (stepped structure).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the field plate of Lee to be in direct contact with first and second thicknesses of the semiconductor material to form ohmic contact as taught by Curatola [0027]-[0028].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights