Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Replacement drawing sheets for figures 3D-3F have been filed by applicant and are only correcting informalities relating to the reference numerals of the originally filed drawings. The drawings were received on 8/. These drawings are entered
Specification
The amendment to the specification filed 8/8/2025 is only correcting informalities without introducing new matter. The amendment is entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 (and dependent claims 13-15 and 18-20 dependent therefrom) and 16 (and dependent claim 17 dependent therefrom) rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation “the second semiconductor chip” in lines 17-18. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 12 is interpreted in the instant Office action as follows: “the second semiconductor chip” is equivalent to “the second semiconductor integrated circuit chip” based on line 11. This interpretation is to be confirmed by applicant in the next office action.
Claim 16 recites the limitation “the second semiconductor chip” in line 18. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 16 is interpreted in the instant Office action as follows: “the second semiconductor chip” is equivalent to “the second semiconductor integrated circuit chip” based on line 12. This interpretation is to be confirmed by applicant in the next office action.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 14 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. More specifically, claim 14 only includes the limitation “wherein the first mass of encapsulating material and the second mass of encapsulating material are made of different materials” which matches verbatim with lines 21-22 of claim 12 from which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 8-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Golwalkar (US 5366933 A) in view of Pei (US 20200211978 A1).
Regarding claim 1, Golwalker discloses a method (Figs. 3 and 10), comprising: attaching a first semiconductor integrated circuit chip (50, Fig. 5) to a first surface of a leadframe (side 1 of leadframe 20), wherein the leadframe includes an array of electrically conductive leads (44, 46); providing a first pattern of electrically conductive formations (56, 58, Fig. 6) coupling the first semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); molding a first mass of encapsulating material onto the first surface of the leadframe to encapsulate and contact both the first semiconductor integrated circuit chip attached thereon and the first pattern of electrically conductive formations coupled to electrically conductive leads in the array of electrically conductive leads (60, Fig. 7); wherein the first mass of encapsulating material provides a first protective encapsulation of the first semiconductor integrated circuit chip and the first pattern of electrically conductive formations (60 completely encapsulates exposed portions of 50, 56, and 58 therefore protective), and wherein a second surface of the leadframe opposed to the first surface of the leadframe is left uncovered by the first mass of encapsulating material (side 2 of leadframe 20 is uncovered by 60); attaching a second semiconductor integrated circuit chip to the second surface of the leadframe left uncovered by the first mass of encapsulating material with the first semiconductor integrated circuit chip and the first pattern of electrically conductive formations encapsulated by the first mass of encapsulating material (90, Fig. 12); providing a second pattern of electrically conductive formations (94, 96, Fig. 13) coupling the second semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); molding a second mass of encapsulating material onto the second surface of the leadframe to encapsulate and contact both the second semiconductor integrated circuit chip attached thereon and the second pattern of electrically conductive formations coupled to electrically conductive leads in the array of electrically conductive leads (110, Fig. 15); wherein the second mass of encapsulating material provides a second protective encapsulation of the second semiconductor integrated circuit chip and the second pattern of electrically conductive formations (110 completely encapsulates exposed portions of 90, 94, and 96 therefore protective).
Illustrated below is Fig. 15 of Golwalkar.
PNG
media_image1.png
389
457
media_image1.png
Greyscale
Golwalker fails to teach a method wherein “the first mass of encapsulating material and the second mass of encapsulating material are made of different materials.” However, Golwalkar teaches the first and second masses of encapsulating materials are separately and sequentially formed upon a same assembly (the sequence of Figs. 9 and 15).
Pei discloses the first mass of encapsulating material and the second mass of encapsulating material are made of different materials (130 and 144 of Fig. 8 have different material properties, i.e., melting point, therefore necessarily having different material compositions; “melting point” [0049]).
Modifying the method of Golwalkar by having the material composition of the first and second masses of encapsulating materials be made of different materials in the same way disclosed by Pei,would arrive at the claimed method and material configuration. Pei provides a teaching to motivate one to modify the method of Golwalkar in that it would protect the first mass of encapsulating material from damage during the performance of the method (“to prevent melting of the sealant” [0049]). Therefore, it would have been obvious to have the claimed method and material configuration thereof because it would protect the first mass of encapsulating material during manufacture. MPEP 2143 (I)(G).
Regarding claim 2, Golwalker in view of Pei discloses the method of claim 1 (Golwalker, Fig. 9), wherein the leadframe comprises a die pad (25) and wherein the electrically conductive leads in the array of electrically conductive leads are arranged around the die pad with separation spaces therebetween (spaces filled by 70 and 72), wherein the first mass of encapsulating material molded onto the first surface of the leadframe having the first semiconductor integrated circuit chip attached thereon at said die pad and coupled to electrically conductive leads in the array of electrically conductive leads via the first pattern of electrically conductive formations penetrates into said separation spaces (penetrates with 70 and 72).
Regarding claim 4, Golwalker in view of Pei discloses the method of claim 1 (Golwalker, Fig. 15), wherein the material of the first mass of encapsulating material has a higher melting temperature than the material of the second mass of encapsulating material (Pei, “144 preferably has a melting point less than the melting point of the sealant 130” [0049]).
Regarding claim 8, Golwalker in view of Pei discloses the method of claim 1 (Golwalker, Fig. 13), wherein: providing the second pattern of electrically conductive formations comprises ultrasonic bonding of the second semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (electrically bonding 90 to 44/46 through 94/96, “ultrasonic”, col. 8, lines 39-49).
Regarding claim 9, Golwalker in view of Pei discloses the method of claim 1 (Golwalker, Fig. 3), further comprising: positioning the leadframe in a first spatial orientation when performing said steps of attaching the first semiconductor integrated circuit chip to the first surface of the leadframe, providing the first pattern of electrically conductive formations and molding the first mass of encapsulating material onto the first surface of the leadframe (the same orientation of side 1/side 2 is maintained through at least Figs. 5-7); and turning the leadframe over with the first semiconductor integrated circuit chip and the first pattern of electrically conductive formations encapsulated by the first mass of encapsulating material to a second spatial orientation, opposite the first spatial orientation (turning over 20 and the components assembled thereon to the opposite orientation of side 2/side 1, Fig. 11); and with the leadframe in said second spatial orientation, performing said steps of attaching the second semiconductor integrated circuit chip to the second surface of the leadframe, providing the second pattern of electrically conductive formations and molding the second mass of encapsulating material onto the second surface of the leadframe (cited Figs. 12, 13, and 15 are shown as subsequent to the turning of Fig. 11).
Regarding claim 10, Golwalker in view of Pei discloses the method of claim 1 (Golwalker, Figs. 5-7), further comprising: supporting the leadframe via a laminar substrate at the second surface of the leadframe opposed to the first surface of the leadframe while performing said steps of attaching the first semiconductor integrated circuit chip to the first surface of the leadframe, providing the first pattern of electrically conductive formations and molding the first mass of encapsulating material onto the first surface of the leadframe (36 with 38 being the laminar substrate); wherein the laminar substrate counters covering of said second surface of the leadframe by the first mass of encapsulating material (Fig. 9 shows 60 stops at 36 and 38 and is prevented from fully encapsulating side 2 of 20, thus “counters”); and separating the laminar substrate from the leadframe subsequent to molding the first mass of encapsulating material onto the first surface of the leadframe (Fig. 11).
Regarding claim 11, Golwalker in view of Pei discloses the method of claim 1 (Golwalker, Fig. 2A), further comprising embedding a heat spreader into at least one of the first mass of encapsulating material and the second mass of encapsulating material (“silver plating…improves the thermal…conduction” thus a heat spreader, col. 4, lines 10-17).
Regarding independent claim 12 as noted in the 112(b) rejection, Golwalker discloses a semiconductor device (Fig. 15), comprising: a first semiconductor integrated circuit chip (50) attached to a first surface of a leadframe (side 1 of leadframe 20, detailed annotation provided in Fig. 5), wherein the leadframe includes an array of electrically conductive leads (44, 46); a first pattern of electrically conductive formations (56, 58, Fig. 6) coupling the first semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); a first mass of encapsulating material molded onto the first surface of the leadframe (60, Fig. 7) to encapsulate and contact both the first semiconductor integrated circuit chip and the first pattern of electrically conductive formations (60 completely encapsulates exposed portions of 50, 56, and 58 therefore protective); wherein a second surface of the leadframe opposed to the first surface of the leadframe is not covered by the first mass of encapsulating material (side 2 of leadframe 20 is uncovered by 60); a second semiconductor integrated circuit chip attached to the second surface of the leadframe which is not covered by the first mass of encapsulating material (90, Fig. 12); a second pattern of electrically conductive formations (94, 96, Fig. 13) coupling the second semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); and a second mass of encapsulating material molded onto the second surface of the leadframe (110, Fig. 15) to encapsulate and contact both the second semiconductor integrated circuit chip and the second pattern of electrically conductive formations (110 completely encapsulates exposed portions of 90, 94, and 96 therefore protective); wherein the second mass of encapsulating material is distinct from the first mass of encapsulating material (110 and 60 are separately formed, therefore distinct)
Golwalkar fails to teach “the first mass of encapsulating material and the second mass of encapsulating material are made of different materials.” However, Golwalkar teaches the first and second masses of encapsulating materials are separately and sequentially formed upon a same assembly (the sequence of Figs. 9 and 15).
Pei the first mass of encapsulating material and the second mass of encapsulating material are made of different materials (130 and 144 of Fig. 8 have different material properties, i.e., melting point, therefore necessarily having different material compositions; “melting point” [0049]).
Modifying the semiconductor device of Golwalkar by having the material composition of the first and second masses of encapsulating materials be made of different materials in the same way disclosed by Pei, would arrive at the claimed encapsulating material configuration. Pei provides a teaching to motivate one to modify the encapsulating material configuration of Golwalkar in that it would protect the first mass of encapsulating material from damage during manufacture (“to prevent melting of the sealant” [0049]). Therefore, it would have been obvious to have the claimed encapsulating material configuration because it would protect the first mass of encapsulating material during manufacture. MPEP 2143 (I)(G).
Regarding claim 13, Golwalker in view of Pei discloses the semiconductor device of claim 12 (Golwalker, Fig. 9): wherein the leadframe comprises a die pad (25) with electrically conductive leads in the array of electrically conductive leads arranged around the die pad with separation spaces therebetween (spaces filled by 70 and 72); and wherein the first mass of encapsulating material penetrates into said separation spaces (penetrates with 70 and 72).
Regarding claim 14, Golwalker in view of Pei discloses the semiconductor device of claim 12, wherein the first mass of encapsulating material and the second mass of encapsulating material are made of different materials (as cited in the claim 12 rejection).
Regarding claim 15, Golwalker in view of Pei discloses the semiconductor device of claim 14 (Golwalkar, Fig. 15), wherein the material of the first mass of encapsulating material preferably has a higher melting temperature than the material of the second mass of encapsulating material (Pei, “144 preferably has a melting point less than the melting point of the sealant 130” [0049]).
Regarding claim 18, Golwalker in view of Pei discloses the semiconductor device of claim 12 (Golwalker, Fig. 13), further comprising an ultrasonic bond between the second pattern of electrically conductive formations of the second semiconductor integrated circuit chip and the electrically conductive leads in the array of electrically conductive leads (electrical bond of 90 to 44/46 through 94/96, “ultrasonic”, col. 8, lines 39-49).
Regarding claim 19, Golwalker in view of Pei discloses the semiconductor device of claim 12 (Golwalker, Fig. 15), wherein the first pattern of electrically conductive formations comprise first wire bonds and the second pattern of electrically conductive formations comprise second wire bonds (wire bonds are the species of electrically conductive formations illustrated).
Regarding claim 20, Golwalker in view of Pei discloses the semiconductor device of claim 12 (Golwalker, Fig. 2A), further comprising a heat spreader embedded in one or more of the first mass of encapsulating material and the second mass of encapsulating material (“silver plating…improves the thermal…conduction” thus a heat spreader, col. 4, lines 10-17).
Claims 5, 7, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Golwalkar in view of Pei and Kessler (US 20200176412 A1).
Regarding independent claim 5, Golwalker discloses a method (Figs. 3 and 10), comprising attaching a first semiconductor integrated circuit chip (50, Fig. 5) to a first surface of a leadframe (side 1 of leadframe 20), wherein the leadframe includes an array of electrically conductive leads (44, 46); providing a first pattern of electrically conductive formations (56, 58, Fig. 6) coupling the first semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); molding a first mass of encapsulating material onto the first surface of the leadframe having the first semiconductor integrated circuit chip attached thereon and coupled to electrically conductive leads in the array of electrically conductive leads via the first pattern of electrically conductive formations (60, Fig. 7); wherein the first mass of encapsulating material provides a first protective encapsulation of the first semiconductor integrated circuit chip and the first pattern of electrically conductive formations (60 completely encapsulates exposed portions of 50, 56, and 58 therefore protective), and wherein a second surface of the leadframe opposed to the first surface of the leadframe is left uncovered by the first mass of encapsulating material (side 2 of leadframe 20 is uncovered by 60); attaching a second semiconductor integrated circuit chip to the second surface of the leadframe left uncovered by the first mass of encapsulating material with the first semiconductor integrated circuit chip and the first pattern of electrically conductive formations encapsulated by the first mass of encapsulating material (90, Fig. 12); providing a second pattern of electrically conductive formations (94, 96, Fig. 13) coupling the second semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); molding a second mass of encapsulating material onto the second surface of the leadframe having the second semiconductor integrated circuit chip attached thereon and coupled to electrically conductive leads in the array of electrically conductive leads via the second pattern of electrically conductive formations (110, Fig. 15); wherein the second mass of encapsulating material provides a second protective encapsulation of the second semiconductor integrated circuit chip and the second pattern of electrically conductive formations (110 completely encapsulates exposed portions of 90, 94, and 96 therefore protective); and providing the first pattern of electrically conductive formations and the second pattern of electrically conductive formations as wire bonding patterns (wire bonds are the species of electrically conductive formations illustrated).
Golwalker fails to teach “the wire bonding patterns for the first pattern of electrically conductive formations and the second pattern of electrically conductive formations are made of different electrically conductive materials”.
Kessler discloses wire bonding patterns in the same field of endeavor (Fig. 16, 1603), and further discloses the wire bonding patterns are made of different electrically conductive materials (110 and 112 for each wire bonding pattern, respectively made from “aluminum…copper” [0143]). Modifying the wire bonding patterns for the first pattern of electrically conductive formations and the second pattern of electrically conductive formations (of Golwalker) by including the material configuration of Kessler would arrive at the claimed configuration. Kessler provides a teaching to motivate one to modify the material configuration in that it would improve manufacturing flexibility (“connecting a bond wire foot in form of a bi- or multimetallic stack enables the usage of all kind of chip top metals, especially existing technologies with their top metallization” [0025]). Therefore, it would have been obvious to have the claimed wire bonding pattern material configuration because it would improve manufacturing flexibility. MPEP 2143 (I)(G).
Regarding claim 7, Golwalker in view of Kessler discloses the method of claim 5 (Golwalker, Fig. 15), wherein the different electrically conductive materials are copper for the wire bonding patterns of the first pattern of electrically conductive formations and aluminum for the wire bonding patterns of the second pattern of electrically conductive formations (Kessler, “aluminum…copper” [0143]; all of the first and second patterns are both aluminum and copper).
Regarding independent claim 16 as noted in the 112(b) rejection, Golwalker discloses a semiconductor device (Golwalkar, Fig. 15), comprising: a first semiconductor integrated circuit chip (50) attached to a first surface of a leadframe (side 1 of leadframe 20, detailed annotation provided in Fig. 5), wherein the leadframe includes an array of electrically conductive leads (44, 46); a first wire bonding pattern of electrically conductive formations (56, 58, Fig. 6) coupling the first semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); a first mass of encapsulating material molded onto the first surface of the leadframe (60, Fig. 7) to provide a protective encapsulation of the first semiconductor integrated circuit chip and the first pattern of electrically conductive formations (60 completely encapsulates exposed portions of 50, 56, and 58 therefore protective); wherein a second surface of the leadframe opposed to the first surface of the leadframe is not covered by the first mass of encapsulating material (side 2 of leadframe 20 is uncovered by 60); a second semiconductor integrated circuit chip attached to the second surface of the leadframe which is not covered by the first mass of encapsulating material (90, Fig. 12); a second wire bonding pattern of electrically conductive formations (94, 96, Fig. 13) coupling the second semiconductor integrated circuit chip to electrically conductive leads in the array of electrically conductive leads (coupled to leads 44, 46 of the array); and a second mass of encapsulating material molded onto the second surface of the leadframe (110, Fig. 15) to provide a protective encapsulation of the second semiconductor integrated circuit chip and the second pattern of electrically conductive formations; wherein the second mass of encapsulating material is distinct from the first mass of encapsulating material (110 completely encapsulates exposed portions of 90, 94, and 96 therefore protective).
Golwalker fails to teach “the first wire bonding pattern of electrically conductive formations and the second wire bonding pattern of electrically conductive formations are made of different electrically conductive materials”.
Kessler discloses wire bonding patterns in the same field of endeavor (Fig. 16, 1603), and further discloses the wire bonding patterns are made of different electrically conductive materials (110 and 112 for each wire bonding pattern, respectively made from “aluminum…copper” [0143]). Modifying the wire bonding patterns for the first and second wire bonding patterns (of Golwalker) by including the material configuration of Kessler would arrive at the claimed configuration. Kessler provides a teaching to motivate one to modify the material configuration in that it would improve manufacturing flexibility (“connecting a bond wire foot in form of a bi- or multimetallic stack enables the usage of all kind of chip top metals, especially existing technologies with their top metallization” [0025]). Therefore, it would have been obvious to have the claimed wire bonding pattern material configuration because it would improve manufacturing flexibility. MPEP 2143 (I)(G).
Regarding claim 17, Golwalker in view of Kessler discloses the semiconductor device of claim 16 (Golwalkar, Fig. 15), wherein the material of the first wire bonding pattern of electrically conductive formations is copper and the material of the second wire bonding pattern of electrically conductive formations is aluminum (Kessler, “aluminum…copper” [0143]; all of the first and second wire bonding patterns are both aluminum and copper).
Response to Arguments
Applicant's arguments filed 8/8/2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “There is no teaching or suggestion in either Golwalker or Pei for the use of two masses of encapsulating material made of different materials to respectively encapsulate and contact two different integrated circuit chips and their electrical connections”. Remarks at pg. 11. Applicant provides similar assertions regarding amended independent claim 12. Remarks at pg. 12.
Examiner’s reply:
The examiner disagrees and finds Golwalker teaching a structure with two encapsulating materials applied separately and in sequence (Golwalker, Figs. 7 and 15), though lacking extensive details regarding material compositions thereof. Pei teaches two encapsulating materials applied separately and in sequence, however, applied to an alternative structure. Pei has been relied upon to teach motivation for modifying the material compositions of the two separately and sequentially applied encapsulating materials (of Golwalker) to be different; wherein having different compositions would protect the firstly applied encapsulating material from damage while applying the secondly applied encapsulating material (Pei, [0049]). The method steps of Golwalker and Pei regarding the separate and sequential application of encapsulating materials are the same; therefore, it is reasonable to expect the same benefit of Pei when the teaching is applied to Golwalker. Accordingly, the references are used herein the same as in the previous Office action and the rejection is maintained in the same way as the previous Office action.
Applicant argues:
Applicant argues with respect to amended claim 5 that “the wire bonding for the two integrated circuit chips use different electrically conductive materials. This is neither taught nor suggested by the combined teachings of Golwalker and Schwab”. Remarks at pg. 12.
Applicant provides similar assertions regarding amended independent claim 16. Remarks at pg. 12.
Examiner’s reply:
Applicant’s arguments with respect to claims 5 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. More specifically, Applicant’s amendments include a combination of limitations that change the scope of the claims (combination of prior claims 1 with 5 and with 6) beyond that which had previously been considered (claim 1 separately with 5 or 6). Accordingly, a new reference is relied upon in the instant Office action (Kessler).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 September 17, 2025